Motorola Cm Radio Uhf2 Information Manual

Controller Theory of Operation2-13
5.8 Normal Microprocessor Operation
For this radio, the µP is configured to operate in one of two modes, expanded and bootstrap. In 
expanded mode the µP uses external memory devices to operate, whereas in bootstrap operation 
the µP uses only its internal memory. In normal operation of the radio the µP is operating in 
expanded mode as described below.
During normal operation, the µP (U403) is operating in expanded mode and has access to 3 
external memory devices;...

2-14THEORY OF OPERATION
5.9 Static Random Access Memory (SRAM)
The SRAM (U402) contains temporary radio calculations or parameters that can change very 
frequently, and which are generated and stored by the software during its normal operation. The 
information is lost when the radio is turned off. 
The device allows an unlimited number of write cycles. SRAM accesses are indicated by the CS 
signal U402 (which comes from U403-CSGP2) going low. U402 is commonly referred to as the 
external RAM as opposed...

Transmit Audio Circuits2-15
7.0 Transmit Audio Circuits
Figure 2-7Transmit Audio Paths
7.1 Microphone Input Path
The radio supports 2 distinct microphone paths known as internal (from control head J2-15) and 
external mic (from accessory connector P1-2) and an auxiliary path (FLAT TX AUDIO, from 
accessory connector P1-5). The microphones used for the radio require a DC biasing voltage 
provided by a resistive network.
The two microphone audio input paths enter the ASFIC CMP at U504-pin 48 (external mic)...

2-16THEORY OF OPERATION
7.1.2 Standard Microphone
Hook Pin is shorted to the hook mic inside the standard Mic, If the mic is out off hook, 3.3V is routed 
to R429 via R458, D401, and it create 0.7V on MIC_SENSE (u.P U403-67) by Voltage Divider 
R429/R430. U403 senses this voltage and sends command to ASFIC_CMP U504 to get GCB3 =‘1’. 
The audio signal is routed from C5045 via U509-3 (Z1), R5072, U507, R5026, C5091, R5014 via 
C5046 to U504- 46 int mic (C5046 100nF create a159Hz pole with U504- 46 int mic...

Transmit Signalling Circuits2-17
8.0 Transmit Signalling Circuits
Figure 2-8Transmit Signalling Path
From a hardware point of view, there are 3 types of signaling:

Sub-audible data (PL / DPL / Connect Tone) that gets summed with transmit voice or 
signaling,

DTMF data for telephone communication in trunked and conventional systems, and

Audible signaling including MDC and high-speed trunking.
Note:All three types are supported by the hardware while the radio software determines which 
signaling type is...

2-18THEORY OF OPERATION
8.2 High Speed Data
High speed data refers to the 3600 baud data waveforms, known as Inbound Signaling Words 
(ISWs) used in a trunking system for high speed communication between the central controller and 
the radio. To generate an ISW, the µP first programs the ASFIC CMP (U504) to the proper filter and 
gain settings. It then begins strobing U504-pin 19 (HSIO) with a pulse when the data is supposed to 
change states. U504’s 5-3-2 State Encoder (which is in a 2-state mode) is...

Receive Audio Circuits2-19
9.0 Receive Audio Circuits
Figure 2-9Receive Audio Paths
9.1 Squelch Detect
The radio’s RF circuits are constantly producing an output at the discriminator (IF IC). This signal 
(DISC AUDIO) is routed to the ASFIC CMP’s squelch detect circuitry input DISC (U504-pin 2). All of 
the squelch detect circuitry is contained within the ASFIC CMP. Therefore from a user’s point of 
view, DISC AUDIO enters the ASFIC CMP, and the ASFIC CMP produces two CMOS logic outputs 
based on the...

2-20THEORY OF OPERATION
9.2 Audio Processing and Digital Volume Control
The receiver audio signal (DISC AUDIO) enters the controller section from the IF IC where it is.DC 
coupled to ASFIC CMP via the DISC input U504-pin 2. The signal is then applied to both the audio 
and the PL/DPL paths
The audio path has a programmable amplifier, whose setting is based on the channel bandwidth 
being received, an LPF filter to remove any frequency components above 3000Hz, and a HPF to 
strip off any sub-audible data...

Receive Signalling Circuits2-21
9.4 Handset Audio
Certain handheld accessories have a speaker within them which require a different voltage level 
than that provided by U502. For these devices HANDSET AUDIO is available at control head 
connector J2 pin18.
The received audio from the output of the ASFIC CMP’s digital volume attenuator is routed to U505 
pin 2 where it is amplified. This signal is routed from the output of the op-amp U505 to J2-pin 18. 
From the control head, the signal is sent directly...

2-22THEORY OF OPERATION
The low speed limited data output (PL, DPL, and trunking LS) appears at U504-pin18, where it 
connects to the µP U403-pin 80.
The low speed data is read by the µP at twice the frequency of the sampling waveform; a latch 
configuration in the ASFIC CMP stores one bit every clock cycle. The external capacitors C5028, 
and C5026 set the low frequency pole for a zero crossings detector in the limiters for PL and HS 
data. The hysteresis of these limiters is programmed based on the...