Motorola Cm Radio Midband 66 88mhz Information Manual
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Commercial SeriesCM Radios Midband (66-88MHz) Service Information Issu e: December 2 003
ii Computer Software Copyrights The Motorola products described in this manual may include copyrighted Motorola computer programs stored in semiconductor memories or other media. Laws in the United States and other countries preserve for Motorola certain exclusive rights for copyrighted computer programs, including the exclusive right to copy or reproduce in any form, the copyrighted computer program. Accordingly, any copyrighted Motorola computer programs contained in the Motorola products described in this manual may not be copied or reproduced in any manner without the express written permission of Motorola. Furthermore, the purchase of Motorola products shall not be deemed to grant, either directly or by implication, estoppel or otherwise, any license under the copyrights, patents or patent applications of Motorola, except for the normal non-exclusive royalty- free license to use that arises by operation of law in the sale of a product.
iii Table of Contents Chapter 1 MODEL CHART AND TECHNICAL SPECIFICATIONS 1.0 CM340/CM360 Model Chart ................................................................................ 1-1 2.0 Technical Specifications ...................................................................................... 1-2 Chapter 2 THEORY OF OPERATION 1.0 Introduction .......................................................................................................... 2-1 2.0 Midband (66-88MHz) Receiver ........................................................................... 2-1 2.1 Receiver Front-End ....................................................................................... 2-1 2.2 Receiver Back-End ......................................................................................... 2-2 3.0 Midband (66-88MHz) Transmitter Power Amplifier ............................................. 2-2 3.1 First Power Controller Stage........................................................................... 2-2 3.2 Power Controlled Driver Stage ....................................................................... 2-3 3.3 Final Stage...................................................................................................... 2-3 3.4 Bi-Directional Coupler.................................................................................... 2-3 3.5 Antenna Switch............................................................................................... 2-3 3.6 Harmonic Filter ............................................................................................... 2-4 3.7 Power Control ................................................................................................. 2-4 4.0 Midband (66-88MHz) Frequency Synthesis........................................................ 2-4 4.1 Reference Oscillator ....................................................................................... 2-4 4.2 Fractional-N Synthesizer ................................................................................ 2-5 4.3 Voltage Controlled Oscillator (VCO) ............................................................... 2-6 4.4 Synthesizer Operation .................................................................................... 2-7 5.0 Controller Theory of Operation ............................................................................ 2-8 5.1 Radio Power Distribution ................................................................................ 2-8 5.2 Protection Devices........................................................................................ 2-10 5.3 Automatic On/Off .......................................................................................... 2-10 5.4 Microprocessor Clock Synthesiser ............................................................... 2-11 5.5 Serial Peripheral Interface (SPI) ................................................................... 2-12 5.6 SBEP Serial Interface ................................................................................... 2-12 5.7 General Purpose I/O..................................................................................... 2-12 5.8 Normal Microprocessor Operation................................................................ 2-13 5.9 Static Random Access Memory.................................................................... 2-14 6.0 Control Board Audio and Signalling Circuits ...................................................... 2-14 6.1 Audio Signalling Filter IC and Compander (ASFIC CMP) ............................ 2-14 7.0 Transmit Audio Circuits ...................................................................................... 2-15 7.1 Microphone Input Path ................................................................................. 2-15 7.2 PTT Sensing and TX Audio Processing ....................................................... 2-16
iv 8.0 Transmit Signalling Circuits ............................................................................... 2-17 8.1 Sub-Audio Data (PL/DPL) ............................................................................ 2-17 8.2 High Speed Data .......................................................................................... 2-18 8.3 Dual Tone Multiple Frequency (DTMF) Data ............................................... 2-18 9.0 Receive Audio Circuits....................................................................................... 2-19 9.1 Squelch Detect ............................................................................................. 2-19 9.2 Audio Processing and Digital Volume Control.............................................. 2-20 9.3 Audio Amplification Speaker (+) Speaker (-) ................................................ 2-20 9.4 Handset Audio .............................................................................................. 2-21 9.5 Filtered Audio and Flat Audio ....................................................................... 2-21 10.0 Receive Audio Circuits ..................................................................................... 2-21 10.1 Sub-Audio Data (PL/DPL) and High Speed Data Decoder .......................... 2-21 10.2 Alert Tone Circuits ........................................................................................ 2-22 Chapter 3 TROUBLESHOOTING CHARTS 1.0 Troubleshooting Flow Chart for Out-of-Lock Receiver (Sheet 1 of 2).................. 3-2 1.1 Troubleshooting Flow Chart for Out-of-Lock Receiver (Sheet 2 of 2) ............ 3-3 2.0 Troubleshooting Flow Chart for 25W Transmitter (Sheet 1 of 4) ......................... 3-4 2.1 Troubleshooting Flow Chart for 25W Transmitter (Sheet 2 of 4).................... 3-5 2.2 Troubleshooting Flow Chart for 25W Transmitter (Sheet 3 of 4).................... 3-6 2.3 Troubleshooting Flow Chart for 25W Transmitter (Sheet 4 of 4).................... 3-7 3.0 Troubleshooting Flow Chart for Synthesizer (Reference Oscillator)................... 3-8 4.0 Troubleshooting Flow Chart for VCO ................................................................... 3-9 5.0 Troubleshooting Flow Chart for Receiver (Sheet 1 of 2) ................................... 3-10 5.1 Troubleshooting Flow Chart for Receiver (Sheet 2 of 2) .............................. 3-11 6.0 Troubleshooting Flow Chart for DC Supply (Sheet 1 of 2) ................................ 3-12 6.1 Troubleshooting Flow Chart for DC Supply (Sheet 2 of 2) ........................... 3-13 Chapter 4 MIDBAND PCB/SCHEMATICS/PARTS LISTS 1.0 Allocation of Schematics and Circuit Boards ....................................................... 4-1 1.1 Midband and Controller Circuits ..................................................................... 4-1 2.0 Midband 1-25W PCB 8489012U01 (Rev. C) / Schematics ................................. 4-3 2.1 Midband 1-25W PCB 8489012U01 (Rev. C) Parts List................................ 4-11
Chapter 1 MODEL CHART AND TECHNICAL SPECIFICATIONS 1.0 CM340/CM360 Model Chart CM Series Midband 66-88 MHz Model Description MDM50FNC9AN2_NCM340 66-88 MHz 1-25W 10-Ch MDM50FNF9AN2_N CM360 66-88 MHz 1-25W 100-Ch Item Description X FUC1601_ S. Tanapa Midband 25W 10 Ch BNC XFUC1603_S. Tanapa Midband 25W 100 Ch BNC X FCN6288_ Control Head XFCN5523_Control Head X X HKN4137_ Battery Power Cable XXHMN3596_Compact Microphone XXGLN7324_ Low Profile Trunnion XX6866546D02_RTTE Leaflet XX 6866537D37_ Safety Leaflet XPMUC1033ASServicing Kit CM340 X FUC1605ASServicing Kit CM360 X = Indicates one of each is required
1-2 MODEL CHART AND TECHNICAL SPECIFICATIONS 2.0 Technical Specifications Data is specified for +25°C unless otherwise stated. General Specification Midband Frequency Range:66-88 MHz Frequency Stability (-30°C to +60°C, 25°C Ref.)±5 PPM Channel Capacity:CM340 - 10 CM360 - 100 Channel Spacing: 12.5/20/25 kHz Power Output:1-25W Power Supply: 13.2Vdc (10.8 - 15.6 Vdc) negative vehicle ground Dimensions (L X W X H)118mm X 169mm X 44mm Weight: Low power (1-25W) 1.02 Kg Operating Temperature-30 to 60 o C Storage temperature -40 to 80 o C Shock and VibrationMeets MIL-STD 810-C,D&E and TIA/EIA 603 Dust Meets MIL-STD 810-C,D&E and TIA/EIA 603 HumidityMeets MIL-STD 810-C,D&E and TIA/EIA 603
Technical Specifications1-3 *Availability subject to the laws and regulations of individual countries.Tr a n s m i t t e r Specification Midband Frequency Stability: +/- 5ppm Modulation Limiting:±2.5 kHz @ 12.5 kHz ±4.0 kHz @ 20 kHz ±5.0 kHz @ 20/25 kHz Current Drain Transmit: 8A (25W) FM Hum and Noise:-40 [email protected] kHz -45 dB@ 20/25 kHz Conducted/Radiated Emissions:-36 dBm < 1 GHz -30 dBm > 1 GHz Adjacent Channel Power-60dB @12.5, -70dB @ 20/25kHz Audio Response: ( 300 to 3000Hz)+1, -3dB Audio Distortion: @ 1000 Hz, 60% Rated Maximum Deviation:3% Typical Receiver Specification Midband Sensitivity (12dBSINAD): (ETS) 0.35µV (12.5kHz) 0.30µV (25kHz) Typical Intermodulation : (ETS)>65dB Adjacent Channel Selectivity: (ETS)70 dB @ 25 kHz 60 dB @ 12.5 kHz Spurious Rejection: (ETS)70 dB Rated Audio: (ETS) (Extended audio with 4 Ohm speaker)4W Internal , 13W External Audio Distortion @ Rated Audio:3% Typical Hum and Noise: -40 dB @ 12.5 kHz -45 dB @ 20/25 kHz Audio Response: ( 300 to 3000Hz)+1, -3dB Conducted Spurious Emission per FCC Part 15:-57 dBm 1 GHz
Chapter 2 THEORY OF OPERATION 1.0 Introduction This Chapter provides a detailed theory of operation for the Midband circuits in the radio. Details of the theory of operation and trouble shooting for the the associated Controller circuits are included in this Section of the manual. 2.0 Midband (66-88MHz) Receiver 2.1 Receiver Front-End The received signal from the antenna connector is filtered by the harmonic filter (common to both receive and transmit) and routed to the front end via the antenna switch. The signal is routed to 2- pole pre-selector filter tuned by a dual varacter diode D2301, and on to the LNA, Q2301. This is followed by a 3dB attenuator and a 2-pole post selector filter, tuned by varactor D2304. The varactor control voltage is generated by a DAC in the ASFIC (U504-6). An inverting op-amp stage (U517) amplifies the control signal to provide 0-8V. Signal RX_FE_TUNE voltage is increased under software control for higher receive frequencies. Note that the same DAC is used to control the transmitter power. The 9V supply to the LNA (Q2301) is turned on by Q4 when RX_EN is high. Q2302 controls the biasing so that Q2301 is operated with a constant collector current (15mA). In Local Mode, attenuator R38 improves the intermodulation performance prior to the first mixer. In Distance Mode, normal operation, R38 is bypassed by diode D1, which is forward biassed by Q1 turning on when the LOC_DIST line from the microprocessor (U403-45) is high. The first mixer is a passive, double-balanced type, consisting of T1, T2 and U1. This mixer provides all of the necessary rejection of the half-IF spurious response. High-side injection at +15 dBm is delivered to the first mixer. The mixer output is then connected to a duplex network which matches its output to the XTAL filter input (FL2201) at the IF frequency of 21.4 MHz. The duplex network terminates into a 50 ohm resistor (R41) at all other frequencies. Figure 2-1Midband Receiver Block Diagram Mixer Xtal Filter Controller Front Filter Antenna First LO 2nd LO Xtal Osc IF AmpSecond Filter25kHzFilter 12.5kHzFilter Phase Shift Element IFIC LNA RX_FE_TUNE 25kHzFilter 12.5kHzFilter Xtal Filter
2-2THEORY OF OPERATION 2.2 Receiver Back End The IF signal from the crystal filter enters the IF amplifier which provides 20 dB of gain and feeds the IF IC (U2) at pin 1. The first IF signal at 21.4 MHz mixes with the second local oscillator (LO) at 20.945 MHz to produce the second IF at 455 kHz. The second LO uses the external crystal Y2. The second IF signal is amplified and filtered by two external ceramic filters (FL4/FL3 for 12.5KHz channel spacing and FL5/FL2 for 25KHz channel spacing). The IF IC demodulates the signal by means of a quadrature detector and feeds the detected audio (via pin 7) to the audio processing circuits. At IF IC pin 5, an RSSI signal is available with a dynamic range of 70 dB. 3.0 Midband Transmitter Power Amplifier (66-88 MHz) The radio’s 25W PA is a three-stage amplifier used to amplify the output from the TX_INJ to the antenna port. All three stages utilize LDMOS technology. The gain of the first stage (U101)and the second stage (Q105) is adjustable and is controlled by pin 7 of U103-2 via U103-3 and U102-1. It is followed by an LDMOS final stage Q100. Figure 2-2Midband Transmitter Block Diagram Devices U101, Q105 and Q100 are surface mounted. When assembled, Q100 is in direct contact with the chassis. Heat spreader M105 ensures good thermal contact for Q105. 3.1 First Power Controller Stage The first stage (U101) is a variable gain integrated circuit containing two LDMOS FET amplifier stages which can provide up to 20dB gain. It amplifies the RF signal from the VCO (TX_INJ). The output power of stage U101 is controlled by a DC voltage applied to pin 1 from the op-amp U103-3, pin 8. The control voltage simultaneously varies the bias of two FET stages within U101. This biasing point determines the overall gain of U101 and therefore its output drive level to Q105, which in turn controls the output power of the PA. Loop Pin Diode Antenna Switch RF JackAntenna Harmonic Filter CouplerPA - F i n a lStag e From VCO (TX_INJ) ControlledStage Bias Temperature Sense SPI BUSASFIC_CMP PA PWR SET PA Driver Controller U103-2Forward