Microvitec Series 3 Colour Displays Monitors Service Manual

							TYRAP POSITIONS ON CABINET BACK COMPONENTSNote: All tyraps tobe fully tight 
						

							___________MODIFICATION FOR IBM/APPLE INTERFACES_________(1)     Remove TR1 (BC337) and replace with TIP 120 as shown.(2)     Remove R1 (6 K8) and replace with 8K2 1/4 watt 5%.(3)      Race a 10 microfarad 35V electrolytic as follows: (i) negative side, to top of existingC4 position (ii)  positive side,  mechanically wrapped around and soldered to left sideof R3. 
						

							SWITCH MODE POWER SUPPLY - DESCRIPTION AND OPERATIONThe power supply is a variable frequency, self oscillating, switching flyback convertor type, providing mainsisolation and three stabilised voltages, of 18V, 124V and 200V.1.       Control Circuit - DescriptionA.       Operating Normally In A Ready State(1)     TR2 turns on a step voltage whose amplitude depends on the instantaneous value of rectified mamsacross T2 primary.(2)     Current in winding and TR2 collector increases in a linear fashion from zero, in which time energy isstored as flux in the transformer.(3)    During this time D22, D23 and D24 are reverse biased and any load energy is supplied by C27, C28.C31 and C26, from  previous cycle.(4)     TR1 performs a control function, supplied from a reference winding on transformer (nominal+30V).(5)     During ON time of TR2. the emitter of TR1 is held at a constant with regard to reference railfrom  D18.(6)    The base of TR1 is fed directly from the reference rail, via R3, VR4 and R5, any voltagechange on the reference arising from a change of voltage at the main output will vary causingthe constant current source, used to charge C16, to vary in sympathy.(7)    C16 charges on the current available from R10. The voltage across C16 increases until it reachesthe gate trigger voltage of TY1. Then TY1 conducts and crow bars base drive to TR2.(8)     TR2 ceases conduction and its collector voltage becomes positive. The dV/dT at TR2 collector, islimited by C17, R12 and D17. As this occurs D22. D23, D24 and D21 become forward biased andstored energy within the transform er is transferred into output capacitors, and their respective loads.(9)     Eventually voltages on D6, D21. D22. D23 and D24 anodes, collapses. TY1 is forced off priorto this stage by negative anode voltage, allowing TR2 to turn on. Full base drive is thensustained by R16.TR2 BASE Fuse in 
						

							TR2 BASE START-UP Fuse out(10)  HT stabilisation(a) HT stabilisation is achieved by controlling the duty cycle of the switching transistor.(b) Increasing load = increased duty cycle and peak collector current.(c) Increasing mains supply * increased operating frequency.(d) HT adjustment is made by VR4.(e) Extra damping for C14. R6 and D7. are required to limit Vce of TR2. 015 and D16 providenegative off drive and base current tracking, L2 optimises storage time of TR2 forminimum  switching losses.(11) Max available power is determined by measuring, peak collector current of TR2, and issensed by R15. If voltage across R15 exceeds voltage across TY1 gate cathode, then TY1conducts turning TR2 off.NOTE: This sequence occurs during start-up, at low mains and under fault conditions. 2.      Start-Up ProcedureA.      Current required at start-up is sm all com pared with base drive current under normal operating conditions.B.      W hen turn on of TR2 occurs  in this manner (once every 20ms) the oscillation becomes self sustaining.R8 continues to supply current, but is swamped by forward base drive from  R16. 
						

							TR2 COLLECTOR Fuse in3.       OverVoltage ProtectionA.      Controlled by a second feedback loop attached to TY1, consisting of:(1)    A zener diode which senses the reference rail voltage and HT voltage proportionally.(2)     If this reference exceeds zener voltage. 020 conducts, fires TY1 and terminates drive to TR2.During which time enough volts are developed across TY2 gate-cathode to causeconduction, and latch on.(3)     Drive to TR2 is stopped until C23 is fully discharged (10ms).(4)     Power supply is off until the next mains start-up pulse.4.      Short Circuit ProtectionA.     Short circuit or over current on any output rail represents an increase in stored energyrequired from T2. therefore an increase in collector current through TR2. detected by R15. Thus TY1 isfired and TR2 turned off.B.      Now operating in Burst Mode, that is, the power supply is initiated under normal start-up conditions, butonly operates for a few switching cycles when the over current protection comes into operationterminating drive to TR2. 
						

							VIDEO INPUT INTERFACE CIRCUIT - DESCRIPTION AND OPERATIONINPUT: Connections are made at PL101-red, green and blue video, sync options 1, 2, 3 and TTL videonormal/invert. All inputs are flashover protected by, resistors and diodes. R,G,B drives are split  in two ways:1.       Test selectable links TL103, R,G,B.2.      To IC101Select Position  1: The input stage is in the linear mode, the video is buffered and level shifted by emitter outputstages. These provide temperature tracking with TR103, 104 and 105 resulting in a stable black level.NOTE: In the linear mode only brightness variations of the video information are possible using VR314.Select Position 2: TR103, 104 and 105 bases are driven by IC101. This option is used when driving from  TTLvideo sources offering primary/secondary colour and black and white drives.NOTE: In the TTL mode, signal to noise immunity of system is very good. IC101 can be used with negative TTLlevel video drives (R,G,B), in order to invert video information.Video inversion is achieved by toggling video polarity select line at. PL101 pin 2 or TL101:Normal -    0VInvert   -  + 5VTTL Mode: Contrast of video information is tracked by varying available potential across open collector load resistors,R114, 115 and 116 which are supplied by TR101 from +12V, the base being driven from the contrast control sliderVR111, R112. C101 form  a low pass fitter and ensure smooth operation of contrast control.CRT Beam Current: Information is fed to D117, 118, from  a constant current source derived from  124V main HT rail.As CRT beam current increases D117, 118 junctions become more negative thus; D117 conducts more heavilycausing voltage to TR106 base to decrease. R136, C105 filter the signal, the derived voltage is emitter followed andsupplies TR103, 104 and 105 emitters directly. Hence increases in CRT beam current, above a preset limit achievingan automatic reduction in picture brightness.NOTE: CRT beam limiting is preset depending on monitor model.Brightness of display in all modes is adjusted by. VR134 enabling parallel adjustment of R,G,B and black levels withina + or -20V range from  nominal:400uA - High and medium resolution 700uA - 14standard resolution TTL/Linear 900uA - 20 standardresolution  TTL/LinearTR102: A fast switching transistor used to derive mixed blanking pulses for flyback blanking of video inform ation. Thebase is driven from a potential divider/mixer network, from a line flyback pulse and a frame flyback pulse. Line flybackis advanced in phase with C225, to allow for transistor switching delays. D107, holds TR102 in a semi-saturationstate. 
						

							TR102 COLLECTOR with 10 to 1 scope probeIC101 is also used to provide the following sync options:Composite negative sync: Fed in on PL101, pin 7, ensure TL102 in non-active position, allowing pin 2 of IC101, to bepulled high where upon IC101 performs a sync inversion and provides an attenuated positive sync waveform for drivingsync separators of IC201, via R201 and TL106.Composite positive sync: Fed in on PL101, pin 7 with TL102 in its grounded position. IC101, now provides an output inphase with input and of suitable amplitude for driving IC201 directly, via R201 and TL106.Separate negative line and field syncs: Ensure TL102 in non-active position, line syncs are fed in on PL101, pin 5.IC101, performs an exclusive OR function, the output being an inverted composite sync waveform.Separate positive line and field syncs: Fed in on PL101, pin 7 in its grounded position. TL106, is switched over toinverse field option. IC101, provides an attenuated and buffered line sync feed for IC201, via R201. Positive field syncinformation is fed directly PL101, pin 3 sync3 input by, TL106(B) and R202. 
						

							LINE TIMEBASE - DESCRIPTION AND OPERATION1.        Line TimebaseA.       Line oscillator function is based on IC201, providing three outputs:(1)      Horizontal drive pulses for control of line output stage.(2)      Vertical sync pulses compatible with synchronisation of IC301 field output IC.(3)      A sandcastle pulse providing burst gate and clamping information.NOTE: This facility is only used with IC TDA3301, currently required by 1 volt 75 ohm linear/PALinput  monitors.2.      Sync SeparatorA.      IC (TDA1180P), incorporates separate noise gated sync separators for line/field syncs, which acceptspositive going sync pulses (or negative going composite video) on pins 8 and 9.B.     Output pulses from the line sync separator are used in conjunction with a sync gate to synchronise lineoscillator in a phase locked loop circuit.3.      Line Oscillator - Phase DetectorsA.       The line oscillator is timed by a network of resistors and capacitors on pins 14 and 1 5 of IC201, usedto derive a pulse of suitable mark space ratio for driving line output stages.B.       IC201 contains two basic control loops, each containing a phase detector.(1) The first phase detector compares output of the line oscillator with the incoming line sync pulse.Phase detector output on pin 13, is filtered and fed to the voltage control input of the oscillator onpin 15.(2)    The second phase detector, compensates for delays introduced by the line output stage andcompares line flyback pulses at pin 6, with oscillator output. Phase detector output consists of a bi-directional current source used to charge/discharge C213 on pin 5. Voltage derived from C213 isused to control a phase shifter, which regulates the phase of the output pulse on pin 3. Pin 5 alsoprovides a line shift function, by offsetting voltage developed across C213. charged from  VR220,R221 and R222 allowing phase shift of+or -1uS, between line scan and video information.(3)    A 7uS gate pulse from the line oscillator, whose phase position is centred around the horizontal syncpulse. The gated pulse is used to control the arrival of sync pulses at the sync phase detector for aduration of 7uS, allowing latching and de-latching of line oscillator. Obtained by a coincidencedetector which compares the phase gate pulse with that of incoming syncs.(4)     When the two signals are not aligned, the coincidence detector is used to switch p.l.l. filter into ashort time constant mode, giving a high input impedance at pin 12, thus increasing sensitivity andloop gain of oscillator. The phase locked loop now has a low noise immunity but has a very widecapture range. W hen aligned coincidence detector activates the time constant switch, causing lowimpedance on pin 12, achieving a lower sensitivity and loop gain, but providing a high degree ofnoise immunity. During the locked condition the p.l.l. operates with a long time constant.NOTE: A short time constant mode, can be achieved manually by connecting the output of thecoincidence detector on pin 11, to ground. Allowing the oscillator to follow rapid fluctuationsin line period, which may occur on some non-standard signals. 
						

							4,      Line Driver StageA.       Horizontal drive pulses from pin 3 (IC201), are D.C. coupled to TR2Q1 and used to control drivertransformer (T201), providing the impedance conversion necessary to provide 600mA forward basecurrent, for saturation of line output transistor (TR202). Ringing is damped by R225 and C214 at TR201turn off, thus limiting its Vce to a safe value. HT supply to the linedriver comes from main HT supply rail, prior to R231 and HT scaninterlock (PL201 pins 5/6; allowing itsoperation to be checked independently of the line output stage.IC201 PIN 3 with 10 to 1 scope probeTR202 COLLECTOR with 100 to 1 scope probe 
						

							5.      Vertical Sync OutputA.       Output of field sync separator is used to drive vertical sync output stage on pin 10 (IC201).B.      In addition, this pulse is used internally to inhibit the first phase detector during the field sync period, thuspreventing top flutter as a result of equalising pulses.6.       Sandcastle PulseA.       Sandcastle pulse is on pin 7 (IC201), used on models with linear interface PCB assembly consistingof two sections.(1)      Upper portion, suitable for burst gate and clamping operations from the horizontal oscillator,thus ensuring an accurate phase relationship with the video information.(2)     Lower portion, derived from a line flyback slice for line blanking