Icom Ic-F3gt/gs Vhf Fm Transceiver Service Manual

							SERVICE
MANUAL
6-9-16, Kamihigashi, Hirano-ku, Osaka, 547-0002, Japan
S-13605II-CD
© 1999 Icom Inc.
VHF FM TRANSCEIVERS 
						

							6-9-16, Kamihigashi, Hirano-ku, Osaka 547-0002, Japan
Phone :  06 6793 5302
Fax :  06 6793 0013
Communication Equipment
Himmelgeister Str. 100, D-40225 Düsseldorf, Germany
Phone : 0211 346047 Fax : 0211 333639
URL : http://www.icomeurope.comUnit 9, Sea St., Herne Bay, Kent, CT6 8LD, U.K.
Phone : 01227 741741 Fax : 01227 741742
URL : http://www.icomuk.co.ukZac de la Plaine, Rue Brindejonc des Moulinais
BP 5804, 31505 Toulouse Cedex, France
Phone : 561 36 03 03 Fax : 561 36 03 00
URL : http://www.icom-france.comCrta. de Gracia a Manresa Km. 14,750
08190 Sant Cugat del Valles Barcelona, SPAIN
Phone : (
93)
 590 26 70 Fax : (
93)
 589 04 46
URL : http://www.icomspain.com

2380 116th Avenue N.E., Bellevue, WA 98004, U.S.A.
Phone : (
425)
 454-8155 Fax : (
425)
 454-1509
URL : http://www.icomamerica.com
Phone : (
425)
 454-7619A.C.N. 006 092 575
290-294 Albert Street, Brunswick, Victoria, 3056, Australia
Phone : 03 9387 0666 Fax : 03 9387 0022
URL : http://www.icom.net.au 6F No. 68, Sec. 1 Cheng-Teh Road, Taipei, Taiwan, R.O.C.
Phone : (02) 2559 1899 Fax : (02) 2559 18743071 #5 Road, Unit 9, Richmond, B.C., V6X 2T4, Canada
Phone : (
604)
 273-7400 Fax : (
604)
 273-1900
URL : http://www.icomcanada.com
INTRODUCTION
DANGER
ORDERING PARTS
REPAIR NOTES
This service manual describes the latest service information
for the 
IC-F3GT and IC-F3GS at the time of publication.
NEVERconnect the transceiver to an AC outlet or to a DC
power supply that uses more than 16 V. Such a connection
could cause a fire hazard and/or electric shock.
DO NOTexpose the transceiver to rain, snow or any liquids.
DO NOTreverse the polarities of the power supply when con-
necting the transceiver.DO NOTapply an RF signal of more than 20 dBm (100mW)to the antenna connector. This could damage the transceiv-
er’s front end.
Be sure to include the following four points when ordering
replacement parts:
1.  10-digit order numbers
2.  Component part number and name
3.  Equipment model name and unit name
4.  Quantity required
0910051872 PCB B-5386B IC-F3GT MAIN UNIT 1 pieces
8810009510 Screw BT M2 x 6 ZK IC-F3GS Chassis 10 piecesAddresses are provided on the inside back cover for your
convenience.
1. Make sure a problem is internal before disassembling  the transceiver.
2.DO NOTopen the transceiver until the transceiver is disconnected from its power source.
3.DO NOTforce any of the variable components. Turn them slowly and smoothly.
4.DO NOTshort any circuits or electronic parts. An insulated turning tool MUSTbe used for all adjustments.
5.DO NOTkeep power ON for a long time when the transceiver is defective.
6.DO NOTtransmit power into a signal generator or a sweep generator.
7.ALWAYSconnect a 40 dB to 50 dB attenuator between the transceiver and a deviation meter or spectrum analyzer when
using such test equipment.
8.READthe instructions of test equipment thoroughly before connecting equipment to the transceiver. To upgrade quality, all electrical or mechanical parts and
internal circuits are subject to change without notice or oblig-
ation.
IC-F3GTIC-F3GS 
						

							TABLE OF CONTENTS
SECTION 1 SPECIFICATIONS
SECTION 2 INSIDE VIEWS
SECTION 3 DISASSEMBLY AND OPTION INSTRUCTIONS
3-1 DISASSEMBLY INSTRUCTION  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 - 1
3-2 OPTIONAL UNIT INSTALLATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 - 2
SECTION 4 CIRCUIT DESCRIPTION
4-1 RECEIVER CIRCUITS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 - 1
4-2 TRANSMITTER CIRCUITS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 - 2
4-3 PLL CIRCUITS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 - 3
4-4 POWER SUPPLY CIRCUITS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 - 3
4-5  CPU PORT CIRCUITS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 - 4
SECTION 5 ADJUSTMENT PROCEDURES 
5-1 PREPARATION  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 - 1
5-2 PLL ADJUSTMENT  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 - 4
5-3 SOFTWARE ADJUSTMENT  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 - 5
SECTION 6 PARTS LIST
SECTION 7 MECHANICAL PARTS AND DISASSEMBLY
SECTION 8 SEMI-CONDUCTOR INFORMATION
SECTION 9 BOARD LAYOUTS
SECTION 10 BLOCK DIAGRAM
SECTION 11 VOLTAGE DIAGRAM 
						

							1 - 1
SECTION 1 SPECIFICATIONS 
Ô Ô
GENERAL
• Frequency coverage : 136.000–150.000 MHz
• Type of emission : 16K0F3E (W-type), 8K50F3E (N-type)
• Number of channels : 32 ch (16 channels ´2 banks: 2-BANK version), 16 ch (16 channel version)
• Power supply requirement : 7.2 V DC (negative ground; supplied battery pack)
• Current drain (approx.) : Transmit at High (5.0 W) 1.6 A
at Low (1.0 W) 700 mA
Receive rated audio 250 mA
stand-by 70 mA
• Frequency stability : ±0.0005 %
• Usable temperature range : –30˚C to +60˚C; –22˚F to +140˚F
• Dimensions 
(projections not included): 54(W) ´ 132(H) ´ 35(D) mm; 2 5⁄32(W) ´ 5 3⁄16(H) ´ 1 3⁄8(D) in.
• Weight 
(with ant., BP-209): 370 g; 13.1 oz.
Ô Ô
TRANSMITTER
• RF output power (at 7.2 V DC) : 5 W / 1 W (High / Low)
(with supplied battery pack)
• Modulation system : Variable reactance frequency modulation
• Maximum frequency deviation : ±5.0 kHz (W-type), ±2.5 kHz (N-type)
• Spurious emissions : 73 dBc typical
• Adjacent channel power : 60 dB typical
• Transmitter audio distortion : Less than 3% at 1 kHz, 40% deviation
• Limitting charact of modulator : 70–100% of max. deviation
• Ext. microphone connector : 3-conductor 2.5(d) mm (
1⁄10”)/2.2 k½
Ô
Ô
RECEIVER
• Receive system : Double conversion superheterodyne system
• Intermediate frequencies : 1st 31.05 MHz
2nd 450 kHz
• Sensitivity : 0.25 µV at 12 dB SINAD (typical)
• Squelch sensitivity : 0.25 µV at threshold (typical)
• Adjacent channel selectivity : 65 dB (typical)
• Spurious response rejection : 70 dB (typical)
• Intermodulation rejection ratio : 70 dB (typical)
• Hum and noise : 40 dB (typical)
• Audio output power 
(at 7.4 V DC): 500 mW typical at 5% distortion with an 8 ½load
• Ext. speaker connector : 3-conductor 3.5(d) mm (
1⁄8”)/8 ½
Specifications are measured in accordance with EIA/TIA-603.
All stated specifications are subject to change without notice or obligation. 
						

							2 - 1
SECTION 2 INSIDE VIEWS
• MAIN UNIT
Power amplifier
(Q1: 2SK2974) Antenna swtching circuit
(D1, D2, D8: MA77)
TOP VIEW BOTTOM VIEW
RF amplifier
(Q12: 3SK293)
VCO circuit 1st mixer
(Q13: 3SK239A) Low-pass filter circuit
TX/RX switch
(D3, D4: MA77) Mic amplifier circuit APC
 IC3A: NJM2902V
 Q37: DTA144EU
FM IF IC
(IC2: TA31136FN(D))
CPU
(IC8: HD64738747H)
EEPROM
(IC7: HN58X2432TI)
D/A converter
(IC10: M62363FP-560C)
PLL reference oscillator
(X1: CR-664 15.3 MHz)
Crystal filter
 FI1: FL-311 [NARROW]
 FL-312 [WIDE]
PLL IC
(IC1: µPD3140GS)
IF amplifier
(Q14: 2SC4215 O)
()
() 
						

							3 - 1
SECTION 3 DISASSEMBLY AND OPTION INSTRUCTIONS
3-1 DISASSEMBLY INSTRUCTION
• REMOVING THE CHASSIS PANEL
1Unscrew 1 nut A, and remove 1 knob B.
2Unscrew 2 screws C.
3Take off the chassis in the direction of the arrow.
4Unplug J6 to separate front panel and chassis.
• REMOVING THE MAIN UNIT
1Remove the searing rubber.
2Unsolder 3 points D, and unscrew 1 nut E.
3Unscrew 4 screws Fand 5 screws G (silver, 2mm) to separate the chassis and the MAIN unit.
4Take off the MAIN unit in the direction of the arrow.
(nickel,2mm) x 2 
Front panelChassis
J6 (Speaker connector)
B
C
A
F(black,2mm) x 2
(silver,2mm) x 6
Shield cover
Guide holes MAIN unit
Sealing rubber
Chassis
FDDG
D
E
G 
						

							3 - 2
3-2 OPTIONAL UNIT INSTALLATIONS
1Remove the option cover.
2Remove the bottom protective paper of spoge.
3Connect one of UT-96, UT-105, UT-109, UT-110, UT-111, and UT-108 optional unit J5.
4Replace the option cover to the chassis-hole.
SPONGE
Parts name : 1556 sponge
Order No. : 8930013545Option cover
Option unit
J5 
						

							4 - 1
SECTION 4 CIRCUIT DESCRIPTION
4-1 RECEIVER CIRCUITS
4-1-1 ANTENNA SWITCHING CIRCUIT
Received signals are passed through the low-pass filter (L1,
L2, C1–C5, C8). The filtered signals are applied to the l⁄4
type antenna switching circuit (D2, D8).
The antenna switching circuit functions as a low-pass filter
while receiving. However, its impedance becomes very high
while D2 and D8 are turned ON. Thus transmit signals are
blocked from entering the receiver circuits. The antenna
switching circuit employs a 
l⁄4type diode switching system.
The passed signals are then applied to the RF amplifier cir-
cuit.
4-1-2 RF CIRCUIT
The RF circuit amplifies signals within the range of frequen-
cy coverage and filters out-of-band signals.
The signals from the antenna switching circuit are amplified
at the RF amplifier (Q12) after passing through the tunable
bandpass filter (L16, L17, D9, D10, C78–C80, C86, C93,
C277). The amplified signals are applied to the 1st mixer cir-
cuit (Q13) after out-of-band signals are suppressed at the
tunable bandpass filter (D11, D12, L18, L19, C91, C92, C94,
C96–C98).
Varactor diodes are employed at the bandpass filters that
track the filters and are controlled by the CPU (IC8) via the
expander IC (IC10) using T1–T4 signals. These diodes tune
the centre frequency of an RF passband for wide bandwidth
receiving and good image response rejection.
4-1-3 1ST MIXER AND 1ST IF CIRCUITS
The 1st mixer circuit converts the received signal into a fixed
frequency of the 1st IF signal with a PLL output frequency.
By changing the PLL frequency, only the desired frequency
will pass through a crystal filter at the next stage of the 1st
mixer.The signals from the RF circuit are mixed at the 1st mixer
(Q13) with a 1st LO signal coming from the VCO circuit to
produce a 31.05 MHz 1st IF signal.
The 1st IF signal is applied to a pair of crystal filters (FI1) to
suppress out-of-band signals. The filtered 1st IF signal is
applied to the IF amplifier (Q14), then applied to the 2nd
mixer circuit (IC2, pin 16).
4-1-4 2ND IF AND DEMODULATOR CIRCUITS
The 2nd mixer circuit converts the 1st IF signal into a 2nd IF
signal. A double conversion superheterodyne system (which
converts receive signals twice) improves the image rejection
ratio and obtains stable receiver gain.
The 1st IF signal from the IF amplifier is applied to the 2nd
mixer section of the FM IF IC (IC2, pin 16), and is mixed with
the 2nd LO signal to be converted into a 450 kHz 2nd IF sig-
nal.
The FM IF IC contains the 2nd mixer, limiter amplifier, quad-
rature detector and active filter circuits. A 2nd LO signal
(30.6 MHz) is produced at the PLL circuit by doubling it’s ref-
erence frequency.
The 2nd IF signal from the 2nd mixer (IC2, pin 3) passes
through a ceramic filter (FI2) to remove unwanted hetero-
dyned frequencies. It is then amplified at the limiter amplifi-
er (IC2, pin 5) and applied to the quadrature detector (IC2,
pins 10, 11) to demodulate the 2nd IF signal into AF signals.
• 2nd IF and demodulator circuits
Mixer
16 Limiter
amp.2nd IF filter
450 kHzPLL IC
IC1
X1
15.3 MHz
IC2 TA31136F12
1st IF from the IF amplifier (Q14)
SD signal to the CPU pin 98 11 10 987 5 3
AF signal DET
R5
X3 R86 C122C121
R88 R87
R83 SQLIN signal from the 
D/A convertor (IC10, pin 23)
R82
C112 C113C116217 16
Active
filter
FI2
Noise
detector
FM
detector
13
NOIS signal to the CPU pin 19
RSSI
Noisecomp.
´2
R84 
						

							4 - 2
4-1-5 AF CIRCUIT
AF signals from the FM IF IC (IC2, pin 9) are applied to the
mute switch (IC4, pin 1) via the AF filter circuit (IC3b, pins 6,
7). The output signals from pin 11 are applied to the AF
power amplifier (IC5, pin 4) after being passed through the
[VOL] control (R143).
The applied AF signals are amplified at the AF power ampli-
fier circuit (IC5, pin 4) to obtain the specified audio level. The
amplified AF signals, output from pin 10, are applied to the
internal speaker (SP1) as the “SP” signal via the [SP] jack
when no plug is connected to the jack.
4-1-6 SQUELCH CIRCUIT
A squelch circuit cuts out AF signals when no RF signals are
received. By detecting noise components in the AF signals,
the squelch switches the AF mute switch.
A portion of the AF signals from the FM IF IC (IC2, pin 9) are
applied to the active filter section (IC2, pin 8) where noise
components are amplified and detected with an internal
noise detector.
The active filter section amplifies noise components. The fil-
tered signals are rectified at the noise detector section and
converted into “NOIS” (pulse type) signals at the noise com-
parator section. The “NOIS” signal is applied to the CPU
(IC8, pin 19).
The CPU detects the receiving signal strength from the
number of the pulses, and outputs an “RMUT” signal from
pin 49. This signal controls the mute switch (IC4) to cut the
AF signal line.
4-2 TRANSMITTER CIRCUITS
4-2-1 MICROPHONE AMPLIFIER CIRCUIT
The microphone amplifier circuit amplifies audio signals with
+6 dB/octave pre-emphasis characteristics from the micro-
phone to a level needed for the modulation circuit.The AF signals from the microphone are applied to the
microphone amplifier circuit (IC3c, pin 10). The amplified AF
signals are passed through the low-pass filter circuit (IC3d,
pins 13, 14) via the mute switch (IC4, pins 4, 3). The filtered
AF signals are applied to the modulator circuit after being
passed through the mute switch (IC4, pins 9, 8).
4-2-2 MODULATION CIRCUIT
The modulation circuit modulates the VCO oscillating signal
(RF signal) using the microphone audio signal.
The audio signals change the reactance of a diode (D6) to
modulate an oscillated signal at the VCO circuit (Q7, Q8).
The oscillated signal is amplified at the buffer-amplifiers (Q4,
Q6), then applied to the T/R switching circuit (D3, D4).
4-2-3 DRIVE/POWER AMPLIFIER CIRCUITS
The signal from the VCO circuit passes through the T/R
switching circuit (D3) and is amplified at the buffer (Q3),
drive (Q2) and power amplifier (Q1) to obtain 5 W of RF
power (at 7.2 V DC). The amplified signal passes through
the antenna switching circuit (D1), and low-pass filter and is
then applied to the antenna connector.
The bias current of the drive (Q2) and the power amplifier
(Q1) is controlled by the APC circuit.
4-2-5 APC CIRCUIT
The APC circuit (IC3a, Q37) protects the drive and the
power amplifiers from excessive current drive, and selects
HIGH or LOW output power.
The signal output from the power detector circuit (D32, D33)
is applied to the differential amplifier (IC3a, pin 2), and the
“T4” signal from the expander (IC10, pin 11), controlled by
the CPU (IC8), is applied to the other input for reference.
• APC  circuit
Q1
Power
amp.Q2
Driver
amp.
IC3a
+–
VCC
RF signal
from PLL
to antenna
T4
TXC
Q37
S5
APC control circuit
Power detector
circuit (D32, D33)
D33 D32L4, C278, C287
LPF 
						

							4 - 3
When the driving current is increased, input voltage of the
differential amplifier (pin 2) will be increased. In such cases,
the differential amplifier output voltage (pin 1) is decreased
to reduce the driving current.
4-3 PLL CIRCUIT
A PLL circuit provides stable oscillation of the transmit fre-
quency and receive 1st LO frequency. The PLL output com-
pares the phase of the divided VCO frequency to the refer-
ence frequency. The PLL output frequency is controlled by
the divided ratio (N-data) of a programmable divider.
The PLL circuit contains the VCO circuit (Q7, Q8). The oscil-
lated signal is amplified at the buffer-amplifiers (Q6, Q5) and
then applied to the PLL IC (IC1, pin 2).
The PLL IC contains a prescaler, programmable counter,
programmable divider and phase detector, etc. The entered
signal is divided at the prescaler and programmable counter
section by the N-data ratio from the CPU. The divided signal
is detected on phase at the phase detector using the refer-
ence frequency.
If the oscillated signal drifts, its phase changes from that of
the reference frequency, causing a lock voltage change to
compensate for the drift in the oscillated frequency.
A portion of the VCO signal is amplified at the buffer-ampli-
fier (Q4) and is then applied to the receive 1st mixer (Q13)
or transmit buffer-amplifier circuit (Q3) via the T/R switching
diode (D3, D4).
4-4 POWER SUPPLY CIRCUITS
VOLTAGE LINE
• PLL circuit
Shift register´2
PrescalerPhase
detector
Loop
filter
Programmable
counter
Programmable
divider
X1
15.3 MHz 30.6 MHz signal
to the FM IF IC DEV signal from the 
D/A convertor (IC10, pin 22)
when transmitting
16
Q7, Q8
VCO circuit
Buffer
Q6Buffer
Q4
Buffer
Q5
3
4
5PLST
SCK
SOto transmitter circuit
to 1st mixer circuit
D4D3
1782
LINE
HV
VCC
5V
T5
R5
S5
OPTDESCRIPTION
The voltage from the attached battery pack.
The same voltage as the HV line (battery volt-
age) which is controlled by the power swtich
([VOL] control).
Common 5 V converted from the VCC line by the
reference regulator circuit (IC6). The output volt-
age is applied to the CPU (IC8), the 5 V regula-
tor circuit (Q18, Q19) and reset circuit (IC11).
5 V for transmitter circuits regulated by the T5
regulator circuit (Q22).
5 V for receiver circuits regulated by the R5 reg-
ulator circuit (Q21).
Common 5 V converted from the VCC line by the
S5 regulator circuit (Q18, Q19).
The same voltage as the 5V line for the optional
HM-46L, EM-71 or HS-51 through a resistor
(R132).