Hitachi C15 Lc880snt Service Manual
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- 31 -INFORMATION OF ICS IC MC78M05 D-PAK Pin No. Pin Name Description Pin No.Pin Name Description 1 Input Output Voltage 3Output Output Voltage 2 GND IC LM1117DTX-3.3 TO-252 Pin No. Pin Name Description Pin No.Pin Name Description 1 Input Output Voltage 3Adi/GND Output Voltage 2 Output IC LM1084ISX-3.3 TO263 Pin No. Pin Name Description Pin No.Pin Name Description 1 Input Output Voltage 3Adi/GND Output Voltage 2 Output IC LM2596S-5.0 TO-263 Pin No. Pin Name Description Pin No.Pin Name Description 1 VIN 4Feed Back 2 Output 5ON/OFF 3 Ground IC SN74CBT3253CDBQR SSOP16 Pin No. Pin Name Description Pin No.Pin Name Description 1 1OE 92A 2 S1 102B1 3 1B4 112B2 4 1B3 122B3 5 1B2 132B4 6 1B1 14S0 7 1A 152OE 8 GND 16VCC IC24LC16BT SOIC08 Pin No. Pin Name Description Pin No.Pin Name Description 1 A0 5SDA 2 A1 6SCL 3 A2 7WP 4 VSS 8VCC IC FDS9933A SO-8 Pin No. Pin Name Description Pin No.Pin Name Description 1 S1 Source Voltage 5D2 Drain-Source Voltage 2 G1 Gate-Source Voltage 6D2 Drain-Source Voltage 3 S2 Source Voltage 7D1 Drain-Source Voltage 4 G2 Gate-Source Voltage 8D1 Drain-Source Voltage IC 24AA02 SOIC08 Pin No. Pin Name Description Pin No.Pin Name Description 1 A0 5SDA 2 A1 6SCL 3 A2 7WP 4 VSS 8VCC
- 32 -IC FSAV330 QS0P16 Pin No. Pin Name Description Pin No.Pin Name Description 1 S 93A 2 1B1 103B2 3 1B2 113B1 4 1A 124A 5 2B1 134B2 6 2B2 144B1 7 2A 15OE 8 GND 16VCC IC 74LCX14 S0IC14 Pin No. Pin Name Description Pin No.Pin Name Description 1 I0 Inputs 8O3 Outputs 2 O0 Outputs 9I3 Inputs 3 I1 Inputs 10O4 Outputs 4 O1 Outputs 11I4 Inputs 5 I2 Inputs 12O5 Outputs 6 O2 Outputs 13I5 Inputs 7 GND Inputs 14VCC IC SST39SF020A PLCC32 Pin No. Pin Name Description Pin No.Pin Name Description 1 AMS 1 - A 0 Address Inputs 5WE# Write Enable 2 DQ7-DQ 0 Data Input/output 6VDD Power Supply 3 CE# Chip Enable 7VSS Ground 4 OE# Output Enable 8NC No Connection IC GM5221 PQFP-208 (DVI Input Port) Pin No. Pin Name Description 113 AVDD_IMB_3.3 Analog VDD(3.3V) for internal biasing gircuits. Must be bypassed with capacitors 114 REXT External termination resistor. A 1% 250Ω, resistor should by connected from this pin to AVDD_IMB 115 AGND_IMB Analog GND for internal biasing circuits. Must be connected directly to the ground plane. 116 VDD_RX2_1.8 VDD(1.8V) for TMDS input pair 2. Must be bypassed with external capacitor to GND_RX2. 117 AGMD_RX2 Analog GND for TMDS input pair 2. Must be connected directly to the analog ground plane. 118 RX2+ TMDS input pair2 119 RX2- TMDS input pair2 120 AVDD_RX2_3.3 Analog VDD(3.3V) for TMDS input pair 2. Must be bypassed with capacitor to AGND_RX2. 121 VDD_RX1_1.8 VDD(1.8V) for TMDS input pair 2. Must be bypassed with external capacitor to GND_RX1. 122 AGND_RX1 Analog GND for TMDS input pair 1. Must be connected directly to the analog ground plane. 123 RX1+ TMDS input pair 1 124 RX- TMDS input pair 1 125 AVDD_RX1_3.3 Analog VDD (3.3V) for TMDS input pair 2. Must be bypassed with to AGND_RX1.INFORMATION OF ICS
- 33 -INFORMATION OF ICS IC GM5221 PQFP-208 (DVI Input Port) Pin No. Pin Name Description 126 VDD_RX0_1.8 VDD (1.8V) for TMDS input pair 2. Must be bypassed with external capacitor to GND_RX0 127 AGND_RX0 Analog GND for TMDS input pair 0. Must be connected directly to the analog ground plane. 128 RX0+ TMDS input pair 0 129 RX0- TMDS input pair 0 130 AVDD_RX0_3.3 Analog VDD (3.3V) for TMDS input pair 2. Must be bypassed with capacitor to AGND_RX0 131 AGND_RXC Analog GND for TMDS input clock pair. Must be connected directly to the analog ground plane. 132 RXC+ TMDS input clock pair 133 RXC- TMDS input clock pair 134 AVDD_RXC_3.3 Analog VDD (3.3V) for TMDS input clock pair. Must be bypassed with 100pF capacitor to AGND_RXC. 136 GND_RXPLL Analog GND for the TMDS receiver internal PLL. Must be connected directly to the analog ground plane. 137 VDD_RXPLL_1.8Analog VDD (1.8V) for the TMDS receiver internal PLL. Must be bypassed with a capacitor to AGND_RXPLL. 138 CLK_OUT Reserved, unconnected. IC GM5221 PQFP-208 (RCLK PLL Pins) Pin No. Pin Name Description 165 GND_RPLL Digital GND for ADC clocking circuit. Must be directly connected to the digital system ground plane. 166 VDD_RPLL_1.8 Digital power (1.8V) for ADC digital logic. Must be bypassed with capacitor to GND1_ADC. 168 AGND_RPLL Analog ground for the Reference DDS PLL. Must be directly connected to the analog system ground plane. 169 XTAL Crystal oscillator output. 170 TCLK Reference clock (TCLK) from the 14.3MHz crystal oscillator. 171 AVDD_RPLL_3.3 Analog VDD (3.3V) IC GM5221 PQFP-208 (Input Video Port) Pin No. Pin Name Description 112 VCLK Video port data clock input. Up to 75Mhz [Input, 5V-tolerant] 111 GPIO23/VDATA0 Input YUV data in 8-bit BT656 or GPIO23:16 if VPORT is disabled. 110 GPIO22/VDATA1 [Bi-Directional, 5V-tolerant] 109 GPIO21/VDATA2 108 GPIO20/VDATA3 107 GPIO19/VDATA4 106 GPIO18/VDATA5 103 GPIO17/VDATA6 102 GPIO16/VDATA7
- 34 -IC GM5221 PQFP-208 (Analog Input Port) Pin No. Pin Name Description 141 AVDD_BLUE_3.3Analog power (3.3V) for the blue channel. Must be bypassed with capacitor to AGND_BLUE pin on system board. 142 BLUE+ Positive analog input for Blue channel. 143 BLUE- Negative analog input for Blue channel. 144 AGND_BLUE Analog ground for the blue channel. Must be directly connected to the analog system ground plane. 145 AVDD_GREEN_3.3 Analog power (3.3V) for the green channel. Must be bypassed with capacitor to AGND_GREEN pin on system board. 146 SOG_MCSS Dedicated Sync-on-Green pin. NOTE: This pin requires the same AC-couple capacitor (if applicable) like the regular RGB input pins. 147 GREEN+ Positive analog input for Green channel. 148 GREEN- Negative analog input for Green channel. NOTE: For SOG support this pin should be pulled down to GND through a 1MΩ , resistor. 149 AGND_GREEN Analog ground for the green channel. Must be directly connected to the analog system ground plane. 150 AVDD_RED_3.3 Analog power (3.3V) for the red channel. Must be bypassed with capacitor to AGND_RED pin on system board. 151 RED+ Positive analog input for Red channel. 152 RED- Negative analog input for Red channel. 153 AGND_RED Analog ground for the red channel. Must be directly connected to the analog system ground plane. 154 AVDD_ADC_3.3 Analog power (3.3V) for ADC Analog blocks that are shared by all three channels. Includes bandgap reference, master biasing and full scale adjust. Must be bypassed with capacitor th AGND_ADC pin on system board. 156 AGND_ADC Analog ground for ADC analog blocks that are shared by all three channels. Includes bandgap reference, master biasing and full scale adjust. Must be directly connected to analog system ground plane. 163 GND1_ADC Digital GND for ADC clocking circuit. Must be directly connected to the digital system ground plane. 164 VDD1_ADC_1.8 Digital power (1.8V) for ADC encoding logic. Must be bypassed with capacitor to GND1_ADC pin on system board. 181 HSYNC/CSYNC ADC input horizontal sync or composite sync input. [Input, Schmitt trigger with 1V hysteresis and 1.65V threshold. 5V-tolerant] 182 VSYNC ADC input vertical sync. [Input, Schmitt trigger with 1V hysteresis and 1.65V threshold. 5V-tolerant]INFORMATION OF ICS
- 35 -INFORMATION OF ICS IC GM5221 PQFP-208 (System Interface) Pin No. Pin Name Description 81 GPIO0 General-purpose input/output signals 82 GPIO1 [Bi-directional, Schmitt trigger, 5V-tolerant] 83 GPIO2 84 GPIO3 85 GPIO4 88 GPIO5 89 GPIO6 90 GPIO7/IRQin General-purpose input/output signals [Bi-directional, Schmitt trigger, 5V- 91 GPIO8/IRQout tolerant] or OCM interrupt and chip status. 92 GPIO9/SCL General-purpose input/output signals [Bi-directional, Schmitt trigger, 5V- 93 GPIO10/SDA tolerant] or master device on serial interface bus. 98 GPIO11/PWM0 General-purpose input/output signals or PWM signals. [Bi-directional, 99 GPIO12/PWM1 Schmitt trigger, 5V-tolerant] 100 GPIO13/PWM2 101 GPIO14/PWM3 69 GPIO15 General-purpose input/output signals [Bi-directional, Schmitt trigger, 5V-tolerant] 77 DDC_SCL_VGA DDC2Bi clock for VGA Port 78 DDC_SDA_VGA DDC2Bi data for VGA Port [internal 10K Ω, pull-up resistor] 79 DDC_SCL_DVI DDC2Bi and HDCP clock for DVI Port 80 DDC_SDA_DVD DC2Bi and HDCP data for DVI Port [internal 10K Ω, pull-up resistor] 178 RESETn Hardware Reset (active low) [Schmitt trigger, 5V-tolerant] Connect to ground with 0.01uF (or larger) capacitor. See section, Chip Initialization, for detail 172 LBADC_VDD_3.3 Analog 3.3V power supply for general-purpose ADC 173 LBADC_IN1 LBADC channel 1 174 LBADC_IN2 LBADC channel 2 175 LBADC_IN3 LBADC channel 3 176 LBADC_RETURN Analog Ground (signal return path) for LBADC channels 1, 2 and 3 177 LBADC_GND Ground 71 HOST_SCL/UART_DI Host input clock or 186 UART Data In or JTAG clock signal. [Input, Schmitt trigger, 5V-Tolerant] 72 HOST_SCL/UART_DO Host input data or 186 UART Data out or JTAG mode signal. [Bi-directional, Schmitt trigger, slew rate limited, 5V-Tolerant] 66 JTAG_TDIJTAG Data input signal. 64 JTAG_TDO JTAG data output signal. 56 JTAG_RESET JTAG reset signal.
- 36 -INFORMATION OF ICS
IC GM5221 PQFP-208 (LVDS Display Interface)
Pin No. Pin Name Description
11 AVDD_LV_E_3.3 Digital Power for LVDS outputs. Connect to digital 3.3V supply.
12 AVSS_LV_E Ground for LVDS outputs.
13 CH3P_LV_E
14 CH3N_LV_E
15 CLKP_LV_E
16 CLKN_LV_E
17 CH2P_LV_E
18 CH2N_LV_E
19 CH1P_LV_E
20 CH1N_LV_E
21 CH0P_LV_E
22 CH0N_LV_E
23 AVSS_LV_E Ground for LVDS outputs.
24 AVDD_LV_E_3.3 Digital Power for LVDS outputs. Connect to digital 3.3V supply.
25 AVSS_LV Ground for LVDS outputs.
26 AVDD_LV_3.3 Analog Power for LVDS outputs. Connect to analog 3.3V supply.
27 AVDD_LV_O_3.3 Digital Power for LVDS outputs. Connect to digital 3.3V supply.
28 AVSS_LV_O Ground for LVDS outputs.
29 CH3P_LV_O
30 CH3N_LV_O
31 CLKP_LV_O
32 CLKN_LV_O
33 CH2P_LV_O
34 CH2N_LV_O
35 CH1P_LV_O
36 CH1N_LV_O
37 CH0P_LV_O
38 CH0N_LV_O
39 AVSS_LV_O Ground for LVDS outputs.
40 AVDD_LV_O_3.3 Digital Power for LVDS outputs. Connect to digital 3.3V supply.
67 PPWR Panel Power Control [Tri-state output, 5V-tolerant]
68 PBIAS PANEL Bias Control (backlight enable) [Tri-state output, 5V- tolerant]
43 RESERVED Reserved, unconnected.
44 RESERVED Reserved, unconnected.
45 RESERVED Reserved, unconnected.
46 RESERVED Reserved, unconnected.
47 RESERVED Reserved, unconnected. (Display Enable for TTL interface)
48 RESERVED Reserved, unconnected. (Display Horizontal Sync for TTL interface)
49 RESERVED Reserved, unconnected. (Display Vertical Sync for TTL interface)
- 37 -INFORMATION OF ICS
IC GM5221 PQFP-208 (TTL Display Interface)
Pin No. Pin Name Description
11 AVDD_LV_E_3.3 Analog Power for TTL outputs. Connect to analog 3.3V supply
12 AVSS_LV_E Ground
13 ER0 Red channel bit 0 Not used.
14 ER1 Red channel bit 1 Not used.
15 ER2 Red channel bit 2 Red channel bit 0
16 ER3 Red channel bit 3 Red channel bit 1
17 ER4 Red channel bit 4 Red channel bit 2
18 ER5 Red channel bit 5 Red channel bit 3
19 ER6 Red channel bit 6 Red channel bit 4
20 ER7 Red channel bit 7 Red channel bit 5
21 EG0 Green channel bit 0 Not used.
22 EG1 Green channel bit 1 Not used.
23 AVSS_LV_E Ground for TTL outputs.
24 AVDD_LV_E_3.3 Digital Power for TTL outputs. Connect to digital 3.3V supply.
25 AVSS_LV Ground for TTL outputs.
26 AVDD_LV_3.3 Digital Power for TTL outputs. Connect to digital 3.3V supply.
27 AVDD_LV_O_3.3 Digital Power for TTL outputs. Connect to digital 3.3V supply.
28 AVSS_LV_O Ground for TTL outputs.
29 EG2 Green channel bit 2 Green channel bit 0
30 EG3 Green channel bit 3 Green channel bit 1
31 EG4 Green channel bit 4 Green channel bit 2
32 EG5 Green channel bit 5 Green channel bit 3
33 EG6 Green channel bit 6 Green channel bit 4
34 EG7 Green channel bit 7 Green channel bit 5
35 EB0 Blue channel bit 0 Not used.
36 EB1 Blue channel bit 1 Not used.
37 EB2 Blue channel bit 2 Blue channel bit 0
38 EB3 Blue channel bit 3 Blue channel bit 1
39 AVSS_LV_O Ground
40 AVDD_LV_O_3.3 Digital Power for TTL outputs. Connect to digital 3.3V supply.
43 EB4 Blue channel bit 4 Blue channel bit 2
44 EB5 Blue channel bit 5 Blue channel bit 3
45 EB6 Blue channel bit 6 Blue channel bit 4
46 EB7 Blue channel bit 7 Blue channel bit 5
47 DEN Display Enable
48 DHS Display Horizontal Sync.
49 DVS Display Vertical Sync.
55 DCLK Display Pixel Clock.
67 PPWR Panel Power Control [Tri-state output, 5V-tolerant]
68 PBIAS Panel Bias Control (backlight enable) [Tri-state output, 5V-tolerant]