Asus S62f Service Guide

                                              BIOS SPECIFICATION            
6-17 
 
Table 5-3. Super I/O GPIO Definition 
PIN# GPI
O 
I/O Type Name Activat
ed 
Level
Description 
23 40 I NC NC N/A 
24 41 I NC NC N/A 
25 42 I NC NC N/A 
27 43 I NC NC N/A 
28 44 I NC NC N/A 
29 45 I NC NC N/A 
30 46 I NC NC N/A 
31 47 I NC NC N/A 
32 10 I NC NC N/A 
33 11 I N/A NC N/A 
34 12 O SIOSMI# Low N/A 
35 13  I NC NC N/A 
36 14 I NC NC N/A 
40 23 I NC NC N/A 
* : NC -> Not Connected, SI -> Selection ID. 
  

                                              BIOS SPECIFICATION            
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6. Devices 
 
6.0 CPU   
 
  The CPU supported by S62F system is Intel mobile Yonah dual core processor. 
  The supported frequency is from 1.66GHz to 2.16GHz. 
 
6.1 NORTH BRIDGE (CALISTOGA) 
 
6.1.1 DRB Registers (dram row boundary registers) 
  The DRAM Row Boundary Register defines the upper boundary address of each pair of DRAM 
rows with granularity of 128MB. The offset of these registers are 100h~103h. The...

                                              BIOS SPECIFICATION            
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  001 -> IRQ10 
  010 -> IRQ11 
  011 -> Reserved 
  100 -> IRQ20(Only available if APIC enabled) 
  101 -> IRQ21(Only available if APIC enabled) 
    110 ->  IRQ22(Only available if APIC enabled) 
    111 ->  IRQ23(Only available if APIC enabled) 
 
  6.2.2.2.2 PIRQ[A,C,D,E,F,G,H] Routing Control
 
 
        PIRQA Routing Control Register 0x60 
        PIRQB Routing Control Register 0x61 
    PIRQC Routing Co ntrol...

                                              BIOS SPECIFICATION            
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6.2.3 IDE Controller 
 
6.2.3.1 Function and Feature
 
 
The ICH7-M IDE controller features two sets of interface signals(Primary and Secondary) that 
can be independently enabled, tri-stated or driven low. 
  The ICH7-M IDE controller supports both legacy mode and native mode IDE interface. In 
native mode, the IDE controller is a fully PCI compliant software interface and does not use 
any legacy I/O or interrupt...

                                              BIOS SPECIFICATION            
6-21 
same register, causing the USB 1.1 controller to see a connect event and the EHC to 
see an ‘electrical’ disconnect event. The UHCI driver and hardware handle the 
connection and initialization process from that point on. The EHCI driver and hardware 
handle the perceived disconnect. 
      4. Configure Flag = 1 and an USB 2.0-capable Device is connected  -  In this case, the USB 2.0 Controller is the owner of the port...

                                              BIOS SPECIFICATION            
6-22 
7. CMOS Setup Utility 
 
 S62F system BIOS allows users to change some system hardware/function settings during POST 
(power on self test) stage, users may hit F2 key to enter SETUP mode in POST, the setup feature is 
categorized into 7 menus described as below: 
 
7.1 MAIN MENU 
 
7.1.1 Main menu: 
Main menu describes system overall information with some user changeable setting, it contains 
below items: 
 
  AMI BIOS:...

                                              BIOS SPECIFICATION            
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7.2 ADVANCED MENU
: 
 
In advanced menu, users can configure I/O device resource such as I/O base, interrupt vector or 
DMA(Direct Memory Access) channel, some auxiliary settings may be changed as well. Detailed I/O device 
settings are described below: 
 
 
 
Core Multi-Processing :[Enable] -> enable/disable dual core function  
Execute Disable Bit :[Enable] -> enable/disable “Execute Disable” function  
IDE...

                                              BIOS SPECIFICATION            
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7.2.1 IDE Configuration: 
  7.2.1.1 Primary Master/Slave IDE
 
 
  At system boot, the Intel Ultra ATA Storage Driver configures each ATA/ATAPI device to transfer 
data at particular transfer modes. These transfer modes are defined by ATA standards, and are either 
Programmed I/O (PIO) or Direct Memory Access (DMA or UltraDMA) type transfers.    The Intel Ultra 
ATA Storage Driver usually configures devices for their...

                                              BIOS SPECIFICATION            
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7.2.2 SuperIO Configuration: 
 
  Users can enable/disable Parallel port function and set Parallel Port mode in this page. The Parallel 
Port modes supported by this system are listed below. 
 
1. SPP/Bi-Directional 
2. EPP/SPP 
3. ECP 
4. ECP/EPP 
  

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7.3 SECURITY MENU: 
 
 BIOS supports two levels of password for security protection: 
Supervisor password
: 
Users may set, change or erase system password, the password data is saved in non-volatile 
device (CMOS), system password check is done during POST(Power On Self Test). The BIOS will 
prompt a dialog message to ask user for password check when:  The system has password stored, and “Password on boot” setting in...