Anaheim Stepper LSILS7082N user manual
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QUADRATURE CLOCK CONVERTER
FEATURES:
• x1, x2 and x4 mode selection
• Up to 16MHz output clock frequency
• INDEX input and output
• UP/DOWN indicator output
• Programmable output clock pulse width
• On-chip filtering of inputs for optical or
magnetic encoder applications.
• TTL and CMOS compatible I/Os
• +4.5V to +10V operation (V
DD - VSS)
• LS7082N (DIP); LS7082N-S (SOIC ) - See Figure 1
INPUT/OUTPUT DESCRIPTION:
V
DD (Pin 1)
Supply Voltage positive terminal.
INDX (Pin 2)
Encoder Index pulses are applied to this input.
RBIAS (Pin 3)
Input for external component connection. A resistor con-
nected between this input and V
SS adjusts the output clock
pulse width (Tow). For proper operation, the output clock
pulse width must be less than or equal to the A, B pulse
separation (T
OW £ TPS).
V
SS (Pin 4)
Supply Voltage negative terminal.
A (Pin 5)
Quadrature Clock Input A. This input has a filter circuit to
validate input logic level and eliminate encoder dither.
x2 (Pin 8)
A low level applied to this input selects x2 mode of opera-
tion. See Table 1 for Mode Selection Truth Table and
Figure 2 for Input/Output timing relationship.
B (Pin 9)
Quadrature Clock Input B. This input has a filter circuit
identical to input A. x4/x1
(Pin 10)
This input selects between x1 and x4 modes of operation.
See Table 1 for Mode Selection Truth Table and Figure 2 for
Input/Output timing relationship.
UP/DN (Pin 11)
The count direction at any instant is indicated at this output.
An UP count direction is indicated by a high, and a DOWN
count direction is indicated by a low (See Figure 2).
DNCK (Pin 12)
This DOWN Clock output consists of low-going pulses gen-
erated when A input lags the B input (See Figure 2).
UPCK (Pin 13)
This UP Clock output consists of low-going pulses gener-
ated when A input leads the B input (See Figure 2).
INDX (Pin 14)
This output consists of low-going pulses generated by a
positive clock transition at the A input when INDX input
is high and B input is low and a negative clock transition
at the B input when INDX input is high and A input is high.
(See Figure 2).
NOTE : All unused input pins must be tied to V
DD or VSS.
DESCRIPTION:
The LS7082N is a CMOS quadrature clock converter. Quad-
rature clocks derived from optical or magnetic encoders, when
applied to the A and B Inputs of the LS7082, are converted to
strings of Up Clocks and Down Clocks. Pulses derived from
the Index Track of an encoder, when applied to the INDX input,
produce absolute position reference pulses which are syn-
chronized to the Up Clocks and Down Clocks. These outputs
can be interfaced directly with standard Up/Down counters for
direction and position sensing of the encoder. April 2006
7082N-041906-1
TABLE 1. MODE SELECTION TRUTH TABLE
x2 Input x4/x1 Input MODE
0 Don’t Care x2
1 0 x1
1 1 x4
LSI/CSI
L SI C o m pute r Sy ste m s, I n c. 12 35 W alt W hit m an Ro ad, M elv ill e, N Y 1 174 7 (631 ) 2 71 -0 40 0 F A X (631 ) 2 7 1-0 4 05
LS7082N
U
L®
A3800
1
2
3
4
5
6 7
LS7082N
UPCK DNCK
UP/DN
x4/x1 B
x2
V
DD (+V)
INDX
RBIAS
V
SS (-V)
A
NC
NC
14
13
12
11
8
9
10
FIGURE 1
PIN ASSIGNMENT - TOP VIEW
LSI INDX
ABSOLUTE MAXIMUM RATINGS:
PARAMETER SYMBOL VALUE UNITS
DC Supply Voltage VDD - VSS 11.0 V
Voltage at any inputVIN VSS - 0.3 to VDD + 0.3 V
Operating temperature TA 0 to + 70 °C
Storage temperature TSTG -55 to + 150 °C
DC ELECTRICAL CHARACTERISTICS:
(All voltages referenced to VSS, TA = 0°
C to 70°
C.)
PARAMETERSYMBOLMINMAXUNITSCONDITION
Supply voltageVDD4.510.0V-
Supply currentIDD- 6.0µAVDD = 10.0V, All
input frequencies = 0Hz
RBIAS = 2MW
x4/x1, x2, INDX Logic LowVIL- 0.3VDDV-
A, B Logic LowVIL-0.6VVDD = 4.5V
-1.0VVDD = 9V
-1.1VVDD = 10V
x4/x1, x2, INDX Logic HighVIH0.7VDD- V -
A, B Logic HighVIH3.1-VVDD = 4.5V
5.0-VVDD = 9V
5.6-VVDD = 10V
ALL OUTPUTS:
Sink CurrentIOL 1.75-mAVDD = 4.5V
VOL = 0.4V5.0-mAVDD = 9V
5.7-mAVDD = 10V
Source CurrentIOH1.0-mAVDD = 4.5V
VOH = VDD - 0.5V2.5-mAVDD = 9V
3.0-mAVDD = 10VTRANSIENT CHARACTERISTICS:
(TA = 0°
C to 70°
C)
PARAMETERSYMBOLMINMAXUNITSCONDITION
A, B inputs:
Validation DelayTvD- 85nsVDD = 10V
-100nsVDD = 9V
-160nsVDD = 4.5V
A, B inputs:
Pulse WidthTPWTVD + TOWInfinitens-
A to B or B to A
Phase DelayTPSTOWInfinitens-
1
A, B frequencyfA, B- 2TPWHz-
Input to Output DelayTDS-120nsVDD = 10V
-150nsVDD = 9V
-235nsVDD = 4.5V
Includes input
validation delay
Output Clock Pulse WidthTOW50-nsSee Fig. 4 & 57082N-012703-2
7082N-041906-3UPCK (x2)
A
B
INDX
UPCK (x1)
DNCK (x1)
DNCK (x2)
UPCK (x4)
INDX
UP/DN
TPW
TDS
TPS
Tow
TDS
FIGURE 2. LS7082N INPUT/OUTPUT TIMING DIAGRAM
DNCK (x4)
MUX
CLOCK
AND
DIRECTION
DECODE
DUAL
ONE-SHOT
DUAL
ONE-SHOT
CURRENT
MIRROR
VDD
FIGURE 3. LS7082N BLOCK DIAGRAM
x2 CLOCK
14
11
13
12
3
5
9
10
8
1
4
2 INDX
A
B
x2
INDX
VSS
FILTER
RBIAS
+V
-V
x4/x1
FILTER
UP/DN
Figure 4. Tow vs RBIAS, k VDD=5V VDD=9V VDD=10.0V 100200300400500 250 500 750 1000 1250 1500 NOTE: Vertical axis is output clock pulse width, Tow, ns ENCODER A CLOCK B CLOCK INDEX 5 9 2 13 12 14 8101 34 RB UPCK DNCK RESET x2x4/x1VDD A B RBIASVSS UPCK DNCK INDX FIGURE 6. A TYPICAL APPLICATION IN x4 MODE VSS VDD LS7082N 5 4 14 16 8 +V 40193 +V INDX VDD=5V VDD=9V VDD=10.0V 25 30 20 15 10 5 24681012 Figure 5. Tow vs RBIAS, M NOTE: Vertical axis is output clock pulse width, Tow, µs The information included herein is believed to beaccurate and reliable. However, LSI Computer Systems,Inc. assumes no responsibilities for inaccuracies, nor forany infringements of patent rights of others which mayresult from its use.7082N-012703-4