Anaheim Integrated Circuit LSILS7366R Spec Sheet
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7366R-041906-11 FIGURE 12. LS7366R BLOCK DIAGRAM CLOCK CONTROL IO DATA CONTROLFILTER MUX MODE CONTROL IO SHIFT REG ÷2 FLAG MASK STRMDR1 MDR0 OTR CNTRDTR (32) I R LOAD CLR RD WR CLR RD FLAGS WR POR EN_MDR1 EN_OTR POR EN_DTR (32) (32) (8)(8) (8) (5) EN_CNTRCMPR FLAG LOGIC SCK RXD/MOSI SS/A B INDEX/ f CKi f CKO VDD VSS POR GEN POR FLAGS LFLAG/ TXD/MIS0 (8) MDR0 ( V- ) ( V+ ) SPI_XMIT/ CNT_EN V+ V+ (8) EN_STR EN_DTR EN_CNTR EN_OTR EN_MDR0 EN_MDR1 EN_STR (8) 6 BUFFER LOAD 8 5 7 4 12 11 10 2 1 13 143 LOAD EN_MDR0 BUFFER DFLAG/9
7366R-021309-12 FIGURE 14. PIC18C TO LS7366R LS7366R MISO MOSI SCK SS/ PIC18CXXX RC3/SCK RC4/SDI RC5/SDO RA5 4 5 6 7 LS7366R 1M 40MHz * Cm *Cm f CKI fCKO FIGURE 13. GENERAL I/O CONNECTIONS ENCODER INDEX/ A B 1 2 10 1211 Vss SS/ SCK INT/ RXD TXD SCK SS/ GND MOSI MISO LFLAG/ 8 6 7 5 4 +V +V +V VDD VDD MCU 3 *NOTE: Cm is chosen according to the following equations: Cm = 2(C L - C P) - 10pF, where C L = manufacturers specified crystal load capacitance. C P = PCB parasitic capacitance seen by the crystal.
;Sample routines for PIC18CXXX interface /***********************************************************************************************************************/ ;Initialize PIC18Cxxx portc in LS7366 compatible SPI ;Setup: master mode, SCK idle low, SDI/SDO datashift on high to low transition of SCK ;SS/ assertion/deassertion made with direct manipulation of RA5 ;Initialize portc CLRF PORTC ;Clear portc CLRF LATC ;Clear data latches MOVLW 0x10 ;RC4 is input, RC3 & RC5 are outputs MOVWF TRISC ;RC3=CLK, RC4=SDI, RC5=SDO BCF TRISA, 5 ;RA5=output BSF PORTA, 5 ;RA5=SS/=high CLRF SSPSTAT ;SMP=0 => SDI data sampled at mid-data BSF SSPSTAT, CKE ;CKE=1 => data shifts on active to idle SCK transitions MOVLW 0x21 ;SPI mode initialization data MOVWF SSPCON ;Master mode, CLK/16, CKP=0 => CLK idles low ;data shifted on active to idle CLK edge /***********************************************************************************************************************/ ; WR_MDR0 BSF PORTA, 5 ;SS/=high BCF PORTA, 5 ;SS/=low MOVLW 0x88 ;LS7366 WR_MDR0 command MOVWF SSPBUF ;Transmit command byte LOOP1 BTFSS SSPSTAT, BF ;Transmission complete with BF flag set? BRA LOOP1 ;No, check again MOVF SSPBUF, W ;Dummy read to clear BF flag. MOVLW 0xA3 ;MDR0 data:fck/2, synchronous index. index=rcntr, x4 MOVWF SSPBUF ;Transmit data LOOP2 BTFSS SSPSTAT, BF ;BF set? BRA LOOP2 ;No, check again BSF PORTA, 5 ;SS/=high /***********************************************************************************************************************/ ;RD_MDR0 BSF PORTA, 5 ;SS/=high BCF PORTA, 5 ;SS/=low MOVLW 0x48 ;LS7366 RD_MDR0 command MOVWF SSPBUF ;Transmit command byte LOOP1 BTFSS SSPSTAT, BF ;BF flag set? BRA LOOP1 ;No, check again MOVWF SSPBUF ;Send dummy byte to generate clock & receive data LOOP2 BTFSS SSPSTAT, BF ;BF flag set? BRA LOOP2 ;No, check again MOVF SSPBUF, W ;Recieved data in WREG. MOVWF RXDATA ;Save received data in RAM BSF PORTA, 5 ;SS/=high 7366R-041906-13