Anaheim Integrated Circuit LSILS7362 User Manual

							BRUSHLESS DC MOTOR COMMUTATOR/CONTROLLER
DESCRIPTION:
The LS7362 is a MOS integrated circuit designed to gener-
ate the signals necessary to control a three phase or four
phase brushless DC motor.  It is the basic building block of
a brushless DC motor controller.  The circuit responds to
changes at the SENSE inputs, originating at the motor po-
sition  sensors,  to  provide  electronic  commutation  of  the
motor windings.  Pulse width modulation (PWM) of low-side
drivers for motor speed control is accomplished through ei-
ther the ENABLE input or through the V TRIP input (Analog
Speed control) in conjunction with the OSCILLATOR input.
Overcurrent circuitry is provided to protect the windings, as-
sociated drivers and power supply.  The LS7362 circuitry
causes the external output drivers to switch off immediately
upon sensing the overcurrent condition, and on again only
when the overcurrent condition disappears and the positive
edge  of  either  the  ENABLE  input  or  the  sawtooth  OS-
CILLATOR  occurs.  This  limits  the  overcurrent  sense  cy-
cling to the chopping rate of the ENABLE input or the saw-
tooth OSCILLATOR.  A positive braking feature is provided
to  effect rapid deceleration.  The  LS7362  is designed for
driving Bipolar and Field Effect Transistors. Because only
low-side drivers are pulse width modulated, the LS7362 is
ideally suited in situations where the integrated circuit inter-
faces with level converters to drive high voltage brushless
DC motors.  By pulse width modulating the low-side drivers
only, the switch losses in the level conversion circuitry for
the high-side drivers is minimized.  Figure 1 indicates how
the level conversion is accomplished.  
1
2
3
4 5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20LSICS1
OUT 1
OUT 2
OUT 3
OUT 4
COMMON
OUT 5
OUT 6
BRAKE
ENABLE CS2
FORWARD/REVERSE
V
DD (-V)
S3
S2
S1
OSCILLATOR
V TRIP
OVERCURRENT SENSE
V
SS (+V)
LS7362
CONNECTION DIAGRAM  - TOP VIEW
STANDARD 20 PIN PLASTIC DIP
The COMMON, Pin 5, is tied to the positive supply rail
and LS7362 Outputs 1, 2, and 3 are used to drive level
converters Q101, Q102 and Q103, respectively. Only the
motor  top  side  drivers  consisting  of  Q107,  Q108  and
Q109 which are connected to the motor power supply,
V
M, will be subject to the high speed switching currents
that  flow  through  the  motor.    The  level  converters  are turned on and off at the slower commutation rate.
INPUT/OUTPUT DESCRIPTION:
COMMUTATION SELECTS  (Pins 1, 20)
These inputs are used to select the proper sequence of
outputs based on the electrical separation of the motor
position sensors.  With both inputs low (logic zero), the
sequence is adjusted for 60° electrical separation, with
CS2 high and CS1 low 120° separation sequence is se-
lected, with CS1 high and CS2 low 240° separation se-
quence is selected and with CS1 and CS2 high the 300°
separation sequence is selected.  Note that in all cases
the  external  output  drivers  are  disabled  for  invalid
SENSE input codes.  Internal pull down resistors are pro-
vided at Pins 1 and 20 causing a logic zero when these
pins are left open.
October  2005
7362-101705-1
LSI/CSI
L SI  C o m pute r Sy ste m s, I n c.   12 35 W alt  W hit m an  Ro ad, M elv ill e, N Y 1 174 7     (631 ) 2 71 -0 40 0   F A X  (631 ) 2 7 1-0 4 05
LS7362
•  LS7362 (DIP); LS7362-S (SOIC); 
   LS7362-TS (TSSOP) - See Connection Diagram
U
L®
A3800
FEATURES:
•  Speed Control by Pulse Width Modulating (PWM) only 
    the low-side drivers reduces switching losses in 
    level converter circuitry for high voltage motors.
•   Open or closed loop motor speed control.
•  +5 to +28 Volt operation (Vss - V
DD).
•  Externally selectable input to output code for 60°,            \
   120°, 240°, or 300° electrical sensor spacing.
•  Three or four phase operation.
•  Analog Speed control.
•  Forward/Reverse control.
•  Output Enable control.
•  Positive Static Braking.
•  Overcurrent Sensing.
•  Six outputs drive switching bridge directly. 
						

							FORWARD/REVERSE (Pin 19)
This pin acts to modify the input to output sequence such
that when brought from high to low or low to high the direc-
tion  of rotation will reverse.  An internal pull up resistor is
provided at Pin 19 causing a logic one when left open.
SENSE INPUTS (Pins 15, 16, 17)
These inputs provide control of the output commutation 
sequence as shown in Table III.  S1, S2, S3 originate in
the position sensors of the motor and must sequence in
cycle code order.  Hall switch pull-up resistors are pro-
vided at Pins 15, 16 and 17.  The positive supply of the
Hall devices should be common to the chip Vss.
BRAKE (Pin 9)
A high level applied to this input unconditionally turns off
outputs 1, 2 and 3 and turns on outputs 4,5 and 6 (See
Figure 1).  Transistors Q101, Q102 and Q103 cut off caus-
ing Q107, Q108 and Q109 to cut off and transistors Q104,
Q105 and Q106 turn on, shorting the windings together,
The BRAKE has priority over all other inputs.  An internal
pull down  resistor is provided at Pin 9 causing no braking
when left open.  (Center- tapped motor configuration re-
quires a power supply disconnect transistor controlled by
the BRAKE signal - See Figure 3.)
ENABLE (Pin 10)
A high level on this input permits the output to sequence
as in Table III, while a low disables all external output driv-
ers.  An internal pull up resistor is provided at Pin 10,
enabling when left open.  Positive edges at this input will
reset the overcurrent flip-flop.
OVERCURRENT SENSE (Pin 12)
This input provides the user a way of protecting the motor
winding, drivers and power supply from an overload 
condition.  The user provides a fractional ohm resistor
between the negative supply and the common emitters of
the NPN drivers.  This point is connected to one end of a
potentiometer (e.g. 100K ohms), the other end of which is
connected to the positive supply.  The wiper pickoff is
adjusted so that all outputs are disabled for currents great-
er than the limit.  The action of the input is to disable all
external output drivers.  When BRAKE exists, OVER-
CURRENT SENSE will be overridden.  The overcurrent
circuitry latches the overcurrent condition.  The latch may
be reset by the positive edge of either the sawtooth OS-
CILLATOR or the ENABLE input.  When using the EN-
ABLE input as a chopped input, the OSCILLATOR pin
should be held at VSS.  When the ENABLE input is held
high, the OSCILLATOR must be used to reset the over-
current latch.
V TRIP (Pin 13)
This pin is used in conjunction with the sawtooth OSC in-
put.  When the voltage level applied to VTRIP is more neg-
ative than the waveform at the OSC input, the low-side
drivers will be enabled as shown in Table 3. When VTRIP
is more positive than the sawtooth OSC waveform the low-
side drivers are disabled. The sawtooth waveform at the
OSC  input typically varies from 0.4Vss  to Vss - 2V.  The
purpose of the V TRIP input in conjunction with theOSCILLATOR is to provide variable speed adjustment for the
motor by means of PWM of the low-side drivers for Vss greater
than 7V. Below Vss = 7V,  the IC may only be used as a com-
mutator (See Note). 
Note:  Below Vss = 7V, the OSC sawtooth amplitude is too
small to allow proper operation of the PWM circuitry.
OSCILLATOR (Pin 14)
A reisistor and capacitor connected to this pin (See Fig. 6) pro-
vide the timing components for a sawtooth OSCILLATOR.  The
signal generated is used in conjunction with V TRIP to provide
PWM for variable speed applications and to reset the over-
current condition.
OUTPUTS 1, 2, 3 (Pins 2, 3, 4)
These open drain outputs are enabled as shown in Table III and
provide base current when the COMMON (Pin 5) is tied to Vss.
These outputs provide commutation only for the high-side driv-
ers.  They are not pulse width modulated to control speed.
OUTPUT 4, 5, 6 (Pins 6, 7, 8)
These open drain outputs are enabled as in Table III and 
provide base current to NPN transistors when the COMMON is
tied to Vss.  They provide commutation and are pulse width
modulated to provide speed control.
COMMON (Pin 5)
The COMMON is connected to Vss for driving low-side drivers
and high-side level converters.
Vss, VDD (Pins 11, 18)   
Supply voltage positive and negative terminals.
TYPICAL CIRCUIT OPERATION:
Figure 1 indicates an application using bipolar power tran-
sistors. The oscillator is used for motor speed control as ex-
plained under V TRIP.  Only low-side drive transistors are
pulse width modulated during speed control.  The outputs turn
on in pairs (See Table III).  For example, two separate paths
are turned on when Q8 and Q4 are on. One path is from the
positive supply through Q8, R1 and the base emitter junction of
Q101. The second is from the positive supply through Q4, R14,
the base emitter junction of Q105 and the fractional Ohm re-
sistor to ground. The current in the first path is determined by
the power supply voltage, the impedance of Q8, the value of
R1 and the voltage drop across the base-emitter junction of
Q101 (0.7V for a single transistor or 1.4V for a Darlington Tran-
sistor). The current in the second path is determined by the
power supply voltage, the impedance of Q4, the value of R14
and the voltage drop across the base-emitter junction of Q105.
Table I provides the recommended value for R1; R2, R3, R13,
R14, and R15 are the same value.
Figure 2 indicates an application where Power FETS are used.
The nominal power supply for the LS7362 in this configuration
is 15V so that the low side N channel Power FET drivers will
have 15V of gate drive.  Resistors R13, R14 and R15 serve to
discharge the gate capacitance during FET turn-off.  The high-
side  P-channel FET drivers use 15V Zener diodes Z1, Z2 and
Z3 to limit the gate drive.  Resistors R8, R10 and R12 are the
gate capacitance discharge resistors. Table II indicates the
minimum value of R13 (= R14 = R15) needed as a function of
output drive voltage for the low-side drivers.7362-072503-2 
						

							MAXIMUM RATINGS:
  PARAMETER        SYMBOL                 VALUE                   UNIT
DC Supply Voltage       Vss - VDD                 +35                     V
  AnyInput Voltage to Vss            VIN                                    -30 to +0.5                     V
  Storage Temperature     TSTG                    -65 to +150                    °C
  Operating Temperature    TA                    -40 to +125                    °C      
DC ELECTRICAL CHARACTERISTICS:
(All Voltages Referenced to VDD, TA = 25°C unless otherwise specified)
SYMBOLMINTYPMAXUNIT
Supply VoltageVSS5-28  V
Supply Current
(Excluding Outputs)IDD-4.56 mA
Input Specifications:
BRAKE, ENABLE, CS1, CS2RIN-150- kW
S1, S2, S3, FORWARD/REVERSE
Voltage (Logic 1)VIHVSS - 1.5-VSS  V
             (Logic 0)VIL0-VSS - 4.0  V
OVERCURRENT SENSE (See Note)
Voltage (Logic 1)VIH(VSS/2) + 0.25-VSS  V
             (Logic 0)VIL0-(VSS/2) - 0.25  V
Oscillator:
Frequency RangeFosc01/RC100 kHz
External Resistor RangeRosc22-1000 kW
NOTE:  Theoretical switching point of the OVERCURRENT SENSE input is one half of the power supply determined by an internal bias
network in manufacturing.  Tolerances cause the switching point to vary plus or minus 0.25V.  After manufacture, the switching point
remains fixed within 10mV over time and temperature.  The input switching sensivity is a maximum of 50mV.  There is no hysteresis on
the OVERCURRENT SENSE input.
TABLE I
 OUTPUT CURRENT LIMITING RESISTOR SELECTION TABLE
         POWER                    OUTPUT CURRENT
      SUPPLY
        (Volts)          20    15    10    7.5    5     2.5     mA
  6**********.24
  9******.43.862.2
12.20.33.62.911.53.3
15.36.56.911.32.24.3Resistance
18*.751.21.62.75.1    (kW)
21**1.52.03.36.2
24**1.82.33.67.5
28***      2.7   4.3    9.1
        *causes excessive power dissipation
               **exceeds max current possible for this voltage  TABLE II
For Power Supply 5 - 28 Volts
R13 (k ohms)                         Output Voltage
10                                  Vss - 0.5
4.0                                 Vss - 1.0
1.5                                 Vss - 2.0
TABLE III
OUTPUT COMMUTATION   SEQUENCE
THREE PHASE OPERATION
SEQUENCE SELECTCS1  CS2CS1  CS2CS1  CS2CS1 CS2FORWARD/REVERSE = 1FORWARD/REVERSE = 0
  0        0          0      1           1        0       1       1
ELECTRICAL SEPARATION      (- 60°-) (- 120°-) (- 240°-)   (- 300°-)OUTPUTS      DRIVERSOUTPUTS        DRIVERS
SENSE INPUTSS1 S2 S3S1 S2 S3S1 S2 S3     S1 S2 S3ENABLED   A      B      C     ENABLED     A       B       C
 0   0   0 0   0   1 0   1   0        0   1   1O1, O5  +        -      OffO2, O4     -        +      Off
 1   0   0 1   0   1 1   1   0   1   1   1O3, O5  Off      -       +O2, O6     Off     +        -  
 1   1   0 1   0   0 1   0   0   1   1   0O3, O4   -        Off    +O1, O6     +      Off       -
 1   1   1 1   1   0 1   0   1   1   0   0O2, O4         -         +      OffO1, O5     +        -      Off 
 0   1   1 0   1   0 0   0   1      0   0   0O2, O6   Off      +       -O3, O5     Off     -         +
 0   0   1 0   1   1 0   1   1   0   0   1O1, O6   +       Off     -  O3, O4     -       Off       +
 0   1   0 0   0   0 0   0   0   0   1   0           ALL DISABLED            ALL DISABLED
 1   0   1 1   1   1 1   1   1   1   0   1     ALL DISABLED            ALL DISABLED
The OVERCURRENT input (BRAKE low) enables external output drivers in normal sequence when more negative than Vss/2 and disables
all external output drivers when more positive than Vss/2.  The OVERCURRENT is sensed continuously, and sets a flip flop which is reset
by the rising edge of the ENABLE input or the sawtooth OSCILLATOR.  (See description under OVERCURRENT SENSE.)  7362-051404-3 
						

							6
12
Output
Encoder
7
8
5
4
3
2
Q106Q105Q104
AL1BL2
L3
R13
R14
R15
Q6Q7Q8
Q3Q4Q5
BRAKE
11
Fractional 
Ohm 
ResistorTO OVERCURRENT
ADJUSTMENT
Vss
Vss
O4
O5
O6
O3
O2
O1
M
O
T
O
R
FIGURE 1. BIPOLAR THREE PHASE OUTPUT DRIVER CIRCUITRY
C
Q107Q108Q109
R16R17R18
R4R5R6
Q101
Q102
Q103
R8
R7
R10
R9
R12
R11
R1
R2
R3
VM
6
12
Output
Encoder
7
8
5
4
3
2
AL1BL2
L3Q6Q7Q8
Q3Q4Q5
BRAKE
11
Fractional 
Ohm 
ResistorTO OVERCURRENT
ADJUSTMENT
Vss
Vss
O4
O5
O6
O3
O2
O1
M
O
T
O
R
FIGURE 2.  POWER FET THREE PHASE OUTPUT DRIVER CIRCUITRY
C
R13R14R15
R4R5R6
Q101
Q102
Q103
R8
R7
R10
R9
R12
R11
R1
R2
R3
VM
Z3Z2Z1
Q104Q105Q106
Q107Q108Q1097362-012703-4 
						

							Vss
-
+13V TRIP
EXT. OSCILLATOR
R6
R2C1
S1
R1
15
Vss
C3
Vss
R3
R4
R5
D1
C2
Vss
R8
LS7362
FROM MOTOR
POSITION
SENSOR
14
C4
R7FIGURE 5
CLOSED-LOOP SPEED CONTROLLER
A closed loop system can be configured by differentiating
one of the motor position sense inputs and integrating only
the negative pulses to form a DC voltage that is applied to
the inverting input of an op-amp.  The non-inverting input
voltage is adjusted with a potentiometer until the resultant
voltage at V TRIP causes the motor to run at desired speed.
The R2-C1 differentiator, the R3-D1 negative pulse trans-
mitter and the R4-C2 integrator form a frequency to voltage
converter.  An increase in motor speed above the desired
speed causes V TRIP to increase which lowers the duty cy-
cle modulation of the oscillator and the resultant motor
speed.  A decrease in speed lowers V TRIP and raises the
duty cycle modulation and the resultant motor speed.  For
proper operation, both R5 and R6  should be greater than
R4, and R4 in turn should be greater than both R2 and R3.
Also the R4-C2  time constant should be greater than the
R2-C1 time constant.  C3 may be added across R6 for   
additional V TRIP smoothing.
BRAKE
MOTOR
SUPPLY
Vss
O68
5COMMON
BRAKE
INPUT
7
O46
9
O5
LS7362FIGURE  3.
SINGLE-ENDED 
DRIVER CIRCUIT
This configuration requires only
one base current limiting resistor
connected from the COMMON
pin to Vss.
FORWARD
REVERSE
IN914
2.2KInputs form SG1731
or UC1637
F/R
LS7362
ENABLE
19
10FIGURE 4.  PRECISION CONTROL
BRUSHLESS DC MOTOR DRIVE
For controlled acceleration and deceleration of motors
in the forward or reverse directions, a motor control 
pulse width modulator circuit such as the SG1731 or
UC1637 can be interfaced with the LS7362.
The logical OR gate made up of the resistor-diode net-
work permits the LS7362 to be enabled when either the
forward or reverse input is high.  By applying the forward
input directly to Pin 19, the motor can only operate in the
forward direction when the forward input is high and only
in the reverse direction when the reverse input is high.
Motor direction is determined by relative pulse widths of
the forward and reverse inputs while acceleration or
deceleration is determined by variations of these widths.
The information included herein is believed to beaccurate and reliable.  However, LSI Computer Systems,Inc.  assumes no responsibilities for inaccuracies, nor forany infringements of patent rights of others which mayresult from its use.7362-012703-5 
						

							OUTPUT
DRIVERS
OUTPUT
ENCODER
INPUT
DECODER
R
S
SAWTOOTH
OSCILLATOR
-
+
 +
POSITIVE
EDGE
DETECTOR
COMMUTATION
SEQUENCE
SELECT LOGIC
LOW-SIDE
DRIVERS
HIGH-SIDE
DRIVERS
 5
6
8
 11
VDD 18
 VSS
GND
COMMON4
+V
1
 20
 19
 15
 16
 17
 9
 10
12
 13
14
»30kHz
 CS1
  CS2
  FWD/REV
  S1
  S2
  S3
BRAKE
 ENABLE
OVERCURRENT
SENSE
  V TRIP
   0.001µF
 33k
+V+V
FIGURE 6.   LS7362 BLOCK DIAGRAM
  R
R
+V
 2
3
  4
     5
6
  7
O3
O4
O5
O6
 -
 O1
 O2
  Q7362-101705-6