Alinco Dr-135 Service Manual

DR-135
Service Manual
CONTENTS
SPECIFICATIONS
1) GENERAL ................................................................ 2
2) TRANSMITTER ........................................................ 2
3) RECEIVER ............................................................... 2
CIRCUIT DESCRIPTION DR-135
1) Receiver System .................................................. 3, 4
2) Transmitter System ............................................... 4, 5
3) PLL Synthesizer Circuit...

2
SPECIFICATIONS
1) GENERAL
Frequency coverage
DR-135T, TG (U.S amature) 118.000 ~ 135.995MHz (AM RX)
136.000 ~ 173.995MHz (RX)
144.000 ~ 147.995MHz (TX)
DR-135E, EG (European amature) 144.000 ~ 145.995MHz (RX, TX)
DR-135TA, TAG (Commercial) 118.000 ~ 135.995MHz (AM RX)
136.000 ~ 173.995MHz (RX, TX)
Operating mode 16K0F3E (Wide mode) 8K50F3E (Narrow mode)
Frequency resolution 5, 8.33, 10, 12.5, 15, 20, 25, 30, 50
Number of memory channels 100
Antenna impedance 50Ω unbalanced
Power requirement 13.8V DC...

3
CIRCUIT DESCRIPTION DR-135
1) Receiver System
The receiver system is a double superheterodyne system with a 21.7MHz first IF and a 450kHz second IF.
1. Front End
The received signal at any frequency in the 136.000MHz  to 173.995MHz range
is passed through the low-pass filter (L116, L115, L114, L113, C204, C203,
C202, C216 and C215) and tuning circuit (L105, L104 and D105, D104), and
amplified by the RF amplifier (Q107). The signal from Q107 is then passed
through the tuning circuit (L103, L102, and...

4
5. Squelch Circuit
The detected output which is outputted from the pin 12 of IC108 is inputted to
pin 19 of IC108 after it was been amplified by IC104:A and it is outputted from
pin 20 after the noise component was been eliminated from the composed
band pass filter in the built in amplifier of the IC, then the signal is rectified by
D106 to convert into DC component. The adjusted voltage level at VR101 is
delivered to the comparator of the CPU.
The voltage is led to pin 2 of CPU and compared with the...

5
2. Power Amplifier Circuit
The transmitted signal is oscillated by the VCO, amplified by the drive amplifier
(IC112) and younger amplifier (Q115), and input to the final power module
(IC110). The signal is then amplified by the final power module (IC110) and led
to the antenna switch (D110) and low-pass filter (L113, L114, L115, L116,
C215, C216, C202, C203 and C204), where unwanted high harmonic waves
are reduced as needed, and the resulting signal is supplied to the antenna.
3. APC Circuit
Part of...

6
6. VCO Shift Circuit
During transmission or the AIR band Reception (118 ~ 136 MHz), the VCO
shift circuit turns ON Q138, change control the capacitance of L123 and safely
oscillates the VCO by means of H signal from pin 16 of IC116.)
4) CPU and Peripheral Circuits
1. LCD Display Circuit
The CPU turns ON the LCD via segment and common terminals with 1/4 the
duty and 1/3 the bias, at the frame frequency is 64Hz.
2. Dimmer Circuit
The dimmer circuit makes the output of pin 13 of CPU (IC1) into “H” level...

7
8. CTCSS, DCS Decoder
The voice band of the AF output signal from pin 1 of IC104:A is cut by sharp
active filter IC104:B and C (VCVS) and amplified, then led to pin 4 of CPU. The
input signal is compared with the programmed tone frequency code in the
CPU. The squelch will open when they match. During DCS, Q108 is ON, C156
is working and cut off frequency is lowered.
5) Power Supply Circuit
When power supply is ON, there is a “L” signal being inputted to pin 39 (PSW) of CPU which enables the CPU to...

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6) M3826M8L***GP (XA0795)
CPU
Terminal Connection
(TOP VIEW) 

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No. Pin Name       Function  I/O PU Logic Description
1 P67/AN7 SMT I - A/D S-meter input
2 P66/AN6 SQL I - A/D Noise level input for squelch
3 P65/AN5 BAT I - A/D Battery voltage input
4 P64/AN4 TIN I - A/D CTCSS tone input/DSC code input
5 P63/SCLK22/AN3 BP1 I - A/D Band plan 1
6 P62/SCLK21/AN2 BP2 I - A/D Band plan 2
7 P61/SOUT2/AN1 DCSW O - Activ high DCS signal mute
8 P60/SIN2/AN0 RE2 I - Activ low Rotary encoder input
9 P57/ADT/DA2 TOUT O - D/A CTCSS tone output/DCS tone output
10 P56/DA1 DOUT O...

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No. Pin Name Function  I/O  PU Logic Description
56 P06/SEG32 S32 O - -
57 P05/SEG31 S31 O - -
58 P04/SEG30 S30 O - -
59 P03/SEG29 S29 O - -
60 P02/SEG28 S28 O - -
61 P01/SEG27 S27 O - -
62 P00/SEG26 S26 O - -
63 P37/SEG25 S25 O - -
64 P36/SEG24 S24 O - -
65 P35/SEG23 S23 O - -
66 P34/SEG22 S22 O - -
67 P33/SEG21 S21 O - -
68 P32/SEG20 S20 O - -
69 P31/SEG19 S19 O - -
70 P30/SEG18 S18 O - -
71 SEG17 S17 O - -
72 SEG16 S16 O - -
73 SEG15 S15 O - -
74 SEG14 S14 O - -
75 SEG13 S13 O - -
76 SEG12 S12 O -...