Alinco Dj-296t Circuit Description Manual
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de-emphasis circuit (R106, R107, C127 and C128) and amplified by the AF amplifier (Q27). The signal is then input to pin 2 of the electronic volume (IC6) for volume adjustment, and output from pin 1. The adjusted signal is sent to the audio power amplifier (IC5) through pin 2 to drive the speaker. 2) Transmitter System 1. Modulator Circuit The audio signal is converted to an electric signal in either the internal or external microphone, and input to the microphone amplifier (IC8). IC8 consists of two operational amplifiers; one amplifier (pins 5, 6 and 7) is composed of pre-emphasis and IDC circuits and the other (pins 1, 2, and 3) is composed of a splatter filter. The maximum frequency deviation is obtained by VR1 and input to the cathode of the varicap (D3) of the VCO, to change the electric capacity in the oscillation circuit. This produces the frequency modulation. 2. Power Amplifier Circuit The transmitted signal is oscillated by the VCO, amplified by the pre-drive IC (IC1) and drive amplifier (Q4), and input to the final amplifier (Q2). The signal is then amplified by the final amplifier (Q2) and led to the antenna switch (D2 and D5) and low-pass filter (L2, L3, L5, C2, C9, C10, C11, C24, and C189), where unwanted high harmonic waves are reduced as needed, and the resulting signal is supplied to the antenna. 3. APC Circuit Part of the transmission power from the low-pass filter is detected by D7, converted to DC, and then amplified by a differential amplifier. The output voltage controls the bias voltage from the source of Q2 and Q4 to maintain the transmission power constant. 3) PLL Synthesizer Circuit 1. PLL The dividing ratio is obtained by sending data from the CPU (IC9) to pin 2 and sending clock pulses to pin 3 of the PLL IC (IC2). The oscillated signal from the VCO is amplified by the buffer (Q5 and Q37) and input to pin 6 of IC2. Each programmable divider in IC2 divides the frequency of the input signal by N according to the frequency data, to generate a comparison
frequency of 5 or 6.25 kHz. 2. Reference Frequency Circuit The reference frequency appropriate for the channel steps is obtained by dividing the 12.8 MHz reference oscillation (X1) by 2048 or 2560, according to the data from the CPU (IC9). When the resulting frequency is 5 kHz, channel steps of 5, 10, 15, 20, 25, 30 and 50 kHz are used. When it is 6.25 kHz, the 12.5 kHz channel step is used. 3. Phase Comparator Circuit The PLL (IC1) uses the reference frequency, 5 or 6.25kHz. The phase comparator in the IC2 compares the phase of the frequency from the VCO with that of the comparison frequency, 5 or 6.25kHz, which is obtained by the internal divider in IC2. 4. PLL Loop Filter Circuit If a phase difference is found in the phase comparison between the reference frequency and VCO output frequency, the charge pump output (pin 8) of IC1 generates a pulse signal, which is converted to DC voltage by the PLL loop filter (C69, C70, C80, C88, R44 and R48) and input to the varicap (D3) of the VCO unit for oscillation frequency control. 5. VCO Circuit A Colpitts oscillation circuit driven by Q3 directly oscillates the desired frequency. The frequency control voltage determined in the CPU (IC9) and PLL circuit is input to the varicaps (D3). This change the oscillation frequency, which is amplified by the VCO buffer (Q5) and output from the VCO unit. 4) CPU and Peripheral Circuits 1. LCD Display Circuit The CPU turns ON the LCD via segment and common terminals with 1/4 the duty and 1/4 the bias, at the frame frequency is 112.5Hz. 2. Display Lamp and Key Lamp Circuit When the LAMP key is pressed, “H” is output form pin 42 of the CPU (IC9) to the bases of Q19, Q24 and Q25. Q19, Q24 and Q25 then turn ON and the LED’s (D17, D18, D20, D21, D22 and D23) light. 3. Reset and Backup When the power form the DC jack or external battery increases from Circuits 0 V to 2.5 or more,
“H” level reset signal is output form the reset IC (IC11) to pin 33 of the CPU (IC9), causing the CPU to reset. The reset signal, however, waits at 100, and does not enter the CPU until the CPU clock (X3) has stabilized. 4. S (Signal) Meter Circuit The DC potential of pin 8 of IC5 is input to pin 1 of the CPU (IC9), converted from an analog to a digital signal, and displayed as the S-meter signal on the LCD. 5. DTMF Encoder The CPU (IC9) is equipped with an internal DTMF encoder. The DTMF signal is output from pin 10, through R179 and R180 (for level adjustment), and then through the microphone amplifier (IC8), and is sent to the varicap of the VCO for modulation. At the same time, the monitoring tone passes through the AF circuit and is output form the speaker. 6. CTCSS Encoder The CPU (IC9) is equipped with an internal tone encoder. The tone signal (67.0 to 250.3 Hz) is output form pin 9 of the CPU to the varicap D4 of the VCO for modulation.