Alinco Dj-190 Service Manual

							DJ-190Service ManualCONTENTS      +SPECIFICATIONS2      +CIRCUIT DESCRIPTION3      +SEMICONDUCTOR DATA9      +EXPLODED VIEW15      +PARTS LIST18      +ADJUSTMENT21      +PCBOARD VIEW26      +CIRCUIT DIAGRAM36     +BLOCK DIAGRAM43ALINCO INCORPORATEDTWIN 21 M.I.D. TOWER  BUILDING 23F, 1-61, 2-CHOME,
SHIROMI CHUO-KU , OSAKA, 540-8580 JAPAN
Tel (81)6-6946-8150 fax (81)6-6946-8175e-mail: [email protected] 
						

							SPECIFICATIONSFrequency Coverage     TX            RX DJ-190T (u.s. Amateur version)144.000 ~ 147.995MHz 135.000 ~ 173.995MHz DJ-190E (European Amateur version)144.000 ~ 145.995MHz 144.000 ~ 145.995MHz DJ-190TA1 (commercial version VHFL)135.000 ~ 155.000MHz 135.000 ~ 173.995MHz DJ-190TA2 (commercial version VHFH)150.000 ~ 173.995MHz 135.000 ~ 173.995MHzChannel Step:5, 10, 12.5, 15, 20, 25, 30kHzstepsMemory Channels:40 ChannelsAntenna Impedance:50ohm unbalancedFrequency Stability:+/-5 ppmMicrophone Input Impedance:2kohm  nominal.Signal Type:F3E (FM)Offset Range:0 ~ 99.995MHzDeviation:15kHz max.TX Output (supply voltage):1.5W (4.8V) / 3.5W (7.2V) / 5W (9.6 ~ 13.8V)RX Sensitivity:12dB SINAD better than - 16dBuRX Selectivity:-6dB/    +/- 12kHzI.F.:(1st) 21.25MHz / (2nd) 450kHzPower Supply Requirements:4.8 ~ 13.8V DC (4.8V DC standard)Current ConsumptionTransmitting: Approx. 1.2 Amp. in High Power at 13.8V DC:SettingReceiving: Squelched Approx. 24mA (BS on)Operating Temperature:-10 ~ +60*C, 14 ~ 140*FDimensions:57(W) x 151(H) x 27(D) mm(with EBP-37N without projections)2 1/4(W) x 6(H) x  1 1/16(D) inchesWeight:Approx. 300gSubaudible Tones (CTCSS) :Encoder installed (50 tones)Page-2 
						

							CIRCUIT DESCRIPTION1) Receiver SystemThe receiver system is a double superheterodyne system with a 21.7 MHzfirst IF and a450 kHz second IF.1. Front EndThe received signal at any frequency in the 130.00- to 173.995-MHz rangeis passed through the low-pass filter (L102, L103, L104, C113, C107, C116,and C114) and tuning circuit (L112 and D107), and amplified by the RFamplifier (Q107). The signal from Q107 is then passed through the tuningcircuit (L109, L110, L111, and varicapsi D104, D105 and D106) andconverted into 21.7 MHz by the mixer (Q106). The tuning circuit, whichconsists of L112, L109, varicaps D107 and D104, Ll110 L111, varicapsD105 and D106, is controlled by the tracking voltage from the CPU so thatit is optimized for the reception frequency. The local signal from the VCO ispassed through the buffer (Q108), and supplied to the source of the mixer(Q106). The radio uses the lower side of the superheterodyne system.2. IF CircuitThe mixer mixes the received signal with the local signal to obtain the sumof and difference between them. The crystal filter (XF101 , XF102) selects21.7 MHz frequency from the results and eliminates the signals of theunwanted frequencies. The first IF amplifier (Q105) then amplifies thesignal of the selected frequency.3. Demodulator CircuitAfter the signal is amplified by the first IF amplifier (Q105), it is input to pin16 of the demodulator IC (IC104). The second local signal of 21.25 MHz(shared with PLL IC reference oscillation), which is oscillated by the internaloscillation circuit in IC102 and crystal (X101), is input through pin 1 ofIC104. Then, these two signals are mixed by the internal mixer in IC104and the result is converted into the second IF signal with a frequency of 450kHz. The second IF signal is output from pin 3 of IC104to the ceramic filter(FL101), where the unwanted frequency band of that signal is eliminated,and the resulting signal is sent back to the IC104 through pins 5 and 7.The second IF signal input via pin 7 is demodulated by the internal limiteramplifier and quadrature detection circuit in IC104, and output as an audiosignal through pin 9.4. Audio CircuitThe audio signal from pin 9 of IC104 is compensated to the audiofrequency characteristics in the de-emphasis circuit (R162, R161, C172,C173) and amplified by the AF amplifier (Q109). The signal is then input topin 2 of the electronic volume (IC103) for volume adjustment, and outputfrom pin 1. The adjusted signal is sent to the audio power amplifier (1C105)through pin 2 to drive the speaker. 5. Squelch CircuitPart of the audio signal from pin 9 of IC104 is amplified by the noise filteramplifier consisting of R176, R186, R177, C179, C183, C191, and C194,and the internal noise amplifier in IC104. The desired noise of the signal isoutput through pin 11 of IC104, to be further amplified by the noise amplifier(Q115). The amplified noise signal is rectified by voltage doublers D109 andinput to pin 4 of CPU (IC5).Page-3 
						

							2) Transmitter SystemThe audio signal is converted to an electric signal in either the internal or 1. Modulator Circuitexternal microphone, and input to the microphone amplifier (IC6). IC6consists of two operational amplifiers; one amplifier (pins 1, 2, and 3) iscomposed of pre-emphasis and IDC circuits and the other (pins 5, 6, and 7)is composed of a splatter filter. The maximum frequency deviation isdetermined to its optimal value by switch circuits consisting of Q9 and Q10and input to the cathode of the varicap of the VCO, to change the electriccapacity in the oscillation circuit. This produces the frequency modulation.2. Power AmplifierThe transmitted signal is oscillated by the VCO, amplified by the pre-drive Circuitamplifier (Q102) and drive amplifier (Q101), and input to the power module(IC101). The signal is then amplified by the power module (IC101) and ledto the antenna switch (D101) and low-pass filter (L102, L103, L104, C113,C107, C116, and C114), where unwanted high harmonic waves arereduced as needed, and the resulting signal is supplied to the antenna.3. APC CircuitPart of the transmission power from the low-pass filter is detected by D103,converted to DC, and then amplified by a differential amplifier. The outputvoltage controls the bias voltage from pin 2 of the power module (IC101) tomaintain the transmission power constant.3) PLL Synthesizer CircuitThe dividing ratio is obtained by sending data from the CPU (IC5) to pin 21.PLLand sending clock pulses to pin 3 of the PLL IC (IC102). The oscillatedsignal from the VCO is amplified by the buffer (Q117) and input to pin 6 ofIC102. Each programmable divider in IC102 divides the frequency of theinput signal by N according to the frequency data, to generate acomparison frequency of 5 or 6.25 kHz.2. Reference FrequencyThe reference frequency appropriate for the channel steps is obtained by Circuitdividing the 21.25 MHz reference oscillation (X101) by 4250 or 3400,according to the data from the CPU (IC5). When the resulting frequency is5 kHz, channel stepsof5, 10, 15, 20, 25 and 30 kHz are used. When it is6.25 kHz, the 12.5 kHz channel step is used.3. Phase ComparatorThe PLL (IC102) uses the reference frequency, 5 or 6.25 kHz. The phase Circuitcomparator in the IC102 compares the phase of the frequency from theVCO with that of the comparison frequency, 5 or 6.25 kHz, which isobtained by the internal divider in IC1024. PLL Loop Fitter CircuitIf a phase difference is found in the phase comparison between thereference frequency and VCO output frequency, the charge pump output(pin 8) of IC102 generates a pulse signal, which is converted to DC voltageby the PLL loop filter and input to the varicap of the VCO unit for oscillationfrequency control.Page-4 
						

							5. VCO CircuitA Colpitts oscillation circuit driven by Q301 directly oscillates the desiredfrequency. The frequency control voltage determined in the CPU (IC5) andPLL circuit is input to the varicaps (D301 and D304). This changes theoscillation frequency, which is amplified by the VCO buffer (Q302) andoutput from the VCO unit.NoteThe oscillation frequency is determined by turning Q301 0N and OFF.Displayed frequenciesQ301TX: 130.00 - 139.995 MHzOFFRX: 130.00 - 161.695 MHzTX: 140.00 - 173.995 MHzONRX: 161.70 - 173.995 MHz4) CPU and Peripheral CircuitsThe CPU turns ON the LCD via segment and common terminals with 1/31. LCD Display Circuitthe duty and 1/3 the bias, at the frame frequency is 85Hz.2. Display Lamp CircuitWhen the LAMP key is pressed, H is output from pin 45 of CPU (IC5) tothe bases of Q1 then turn ON and the LEDs (D1, D3) Bight.3. Reset and BackupWhen the power from the DC jack or external battery increases from 0 V to Circuits2.5 or more, H level reset signal is output from the reset IC (IC2) to pin 35of the CPU (IC5), causing the CPU to reset. The reset signal. however,waits at C6 and R98, and does not enter the CPU until the CPU clock (X1)has stabilized. When the external power drops to 3.2 V or below, the outputsignal from the backup IC (IC3), which has been input to pin 34 of the CPU,changes from H to L level. The CPU will then be in the backup state.4. S(Signal)Meter CircuitThe DC potential of pin 13 of IC104 is input to pin 3 of the CPU (IC5),converted from an analog to a digital signal, and displayed as the S-metersignal on the LCD.5. Tone EncoderThe CPU (IC5) is equipped with an internal tone encoder. The tone signal(67.0 to 254.1 Hz) is output from pin 11 of the CPU to the varicap of theVCO for modulation.Page-5 
						

							5) CPU Terminal Functions: M38267M8L (XA413)
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							No.Pin NameSignalI/0LogicDescriptionNo.Pin NameSigna1I/0LogicDescription1C1C1---51P15/SEG39F/KEYIActive lowFunction key input2VL1VL1IA/DLCDpowersupply52P14/SEG38K10I-3P67/AN7SMTIA/DS-meterinput53P13/SEG37K11I-4P66/AN6SQLIA/DNoise level input for squelch54P12/SEG36K12I-5P65/AN5BATIA/DLow battery detection input55P11/SEG35K13l-6P64/AN4BP5IA/DBand plan556P11/SEG34K14I-Key matrix input7P63/CLK22/AN3BP4IBand plan457P07/SEG33SFTO-VCO frequency range change8P62/CLK21/AN2ULIActivehighPLL unlock signal input58P06/SEG32SDOActive lowSigna detection output9P61/SOUT2/AN1BP1,2IA/DBand plans 1 and 259P05/SEG31AFCOActive highAF tone control output10P60/SIN2/ANOMOMIActivelowMonitor key input60P04/SEG30DA4O-11P57/ADT/DA2CTOUTOD/ACTCSS tone output61P03/SEG29DA3O-12P56/AD1DTOUTOD/A62P02/SEG28DA2O-DA converter for electronic volume and output power13P55/CNTR1TSQDIActivelowCTCSS tone detection input63P01/SEG27DA1O-14P54/CNTROBEPOPulseBeep tone output/Band plan 364P00/SEG26DA0O-15P53/RTP1STB2I/OActive low/pulseCTCSS unit detection/Strobe signal to CTCSS unit65P37/SEG25S25O-16P52/RTP0MUTEI/OActivehighMicrophone mute66P36/SEG24S24O-17P51/PWM1CLKOPulseSerial clock output for PLL, CTCSS67P35/SEG23S23O-18P50/PWM0DATAOPulseSerial data output for PLL CTCSS68P34/SEG22S22O-19P47/SRDY1ACKI/0PulseBand plan 669P33/SEG21S21O-20P46/SCLK1STB1OPulseStrobe for PLL IC70P32/SEG20S20O-21P45/TXD1UTXOPulseUART data transmission output71P31/SEG19S19O-22P44/RXD1URXIPulseUART data reception input72P30/SEG18S18O-23P43/D/TOUTTBSTOPulseTone burst (1750Hz) output (European version)73SEG17S17O-24P42/INT2RE2IActivelow74SEG16S16O-25P41/1NT1RE1IActivelowRotary encoder lnput75SEG15S15O-26P40PTTIActivehighPTT input76SEG14S14O-27P77DSWOActivelow77SEG13S13O-28P76STDI/OActivehighDeviation adjustment during transmission78SEG12S12O-LCD segment signal29P75DSDIPulseDeviation adjustment during transmission79SEG11S11O-30P74T3COActive lowTX power ON/OFF output80SEG10S10O-31P73P3COActive lowPLL power ON/OFF output81SEG9S9O-32P72AFPOActivelowAFAMP power ON/OFF output82SEG8S8O-33P71R3COActivelowRX power ON/OFF output83SEG7S7O-34P70/INT0BUIActivelowBackup signal detection input84SEG6S6O-35RESETRSTIActivelowResetinput85SEG5S5O-36XCINXCIN---86SEG4S4O-37XCOUNTXCOUT---87SEG3S3O-38XINXIN--Main clock input88SEG2S2O-39XOUTXOUT--Main clock output89SEG1S1O-40VSSGND--CPU ground90SEG0SOO-41P27PSWIActivelowPower switch input91VCCVDD--CPU power terminal42P26SCLOPulseSerial clock for EEPROM92VREFVREF--AD converter power supply43P25C3COActivehighC3 power ON/OFF output93AVSSAVSS--AD converter ground44P24SDAOPulseSerial data for EEPROM94COM3COM3---45P23LMPOActivehighLamp ON/OFF95COM2COM2O-LCD COM2 output46P22T/KEYIActivelowTone burst/LPTT input96COM1COM1O-LCD COM1 output47P21K00I/O-Band plan BP7 input97COM0COM0O-LCD COM0 output48P20K01O-Key matrix output98VL3VL3I-LCD power supply49P17K02O-99VL2VL2I-LCD power supply50P16K03O-100C2I--Page-7Page-8