Acer Aspire 7730g Service Guide

Chapter 4141
MediaTouch Button Failure
If the Acer MediaTouch buttons fail, perform the following actions one at a time to correct the problem. Do not 
replace a non-defective FRUs:
Fingerprint Reader Failure
If the Fingerprint Reader fails, perform the following actions one at a time to correct the problem. Do not 
replace a non-defective FRUs: 

142Chapter 4
Thermal Unit Failure
If the Thermal Unit fails, perform the following actions one at a time to correct the problem. Do not replace a 
non-defective FRUs:
HDTV Switch Failure
If the HDTV Switch fails, perform the following actions one at a time to correct the problem. Do not replace a 
non-defective FRUs: 

Chapter 4143
External Mouse Failure
If an external Mouse fails, perform the following actions one at a time to correct the problem. 
1.Try an alternative mouse.
2.If the mouse uses a wireless connection, insert new batteries and confirm there is a good connection. See 
the mouse user manual.
3.If the mouse uses a USB connection, try an alternate USB port.
4.Try an alternative program to verify mouse operation. Reinstall the program experiencing mouse failure.
5.Restart the computer.
6.Remove any recently...

144Chapter 4
Intermittent Problems
Intermittent system hang problems can be caused by a variety of reasons that have nothing to do with a 
hardware defect, such as: cosmic radiation, electrostatic discharge, or software errors. FRU replacement 
should be considered only when a recurring problem exists.
When analyzing an intermittent problem, do the following:
1.Run the advanced diagnostic test for the system board in loop mode at least 10 times.
2.If no error is detected, do not replace any FRU.
3.If any...

Chapter 4145
POST Codes Tables
These tables describe the chipset and core POST codes, functions, phases, and components for the POST. 
Chipset POST Codes
The following table details the chipset POST codes and functions used in the POST.
POST CodeFunctionPhaseComponent
0xA0 MRC Entry PEI chipset/MRC
0x01 Enable MCHBAR PEI chipset/MRC
0x02 Check ME existence PEI chipset/MRC
0x03 Check for DRAM initialization interrupt and reset fail PEI chipset/MRC
0x04 Determine the system Memory type based on first...

146Chapter 4
0x32 Program the Egress port timings PEI chipset/MRC
0x33 Program the Memory IO registers PEI chipset/MRC
0x34 Perform steps required before JEDEC PEI chipset/MRC
0x35 Perform JEDEC memory initialization for all memory 
rowsPEI chipset/MRC
0x36 Setup DRAM control register for normal operation 
and enablePEI chipset/MRC
0x37 Do ZQ calibration for DDR3 PEI chipset/MRC
0x38 Perform final Dra/Drb programming, Set the mode of 
operation for the memory channelsPEI chipset/MRC
0x39 Set Enhanced...

Chapter 4147
Core POST Codes
The following table details the core POST codes and functions used in the POST. 0xF3 #define MEM_ERR_RCVEN_FINDCENTER 
(CalibrateRcvenForGroup)PEI chipset/MRC
0xFZ #define MEM_ERR_TYPE (S11, S04) PEI chipset/MRC
0xF5 #define MEM_ERR_RAWCARD (S11) PEI chipset/MRC
0xFA #define MEM_ERR_SFF (ProgWrioDll) PEI chipset/MRC
0xFB #define MEM_ERR_THERMAL (ProgramThrottling) PEI chipset/MRC
0xA0xx Launch BIOS ACMSclean PEI chipset/TXT
0xA4xx Launch BIOS ACMScheck PEI chipset/TXT
0xE5...

148Chapter 4
0x82 Initialize the CPU Crisis Recovery Core
0x89 Set Huge Segment Crisis Recovery Core
0x83 Initialize system timer Crisis Recovery Core
0x84 Initialize system I/O Crisis Recovery Core
0x88 Initialize Multi Processor Crisis Recovery Core
0x8A Initialize OEM special code Crisis Recovery Core
0x8B Initialize PIC and DMA Crisis Recovery Core
0x8C Initialize Memory type Crisis Recovery Core
0x8D Initialize Memory size Crisis Recovery Core
0x8F Initialize SMM Crisis Recovery Core
0x90 System...

Chapter 4149
0x09 TCG log event failed DXE TCG
0x09 Setup event log failed DXE TCG
0x12 TIS set active locality failed DXE TCG
0x12 TIS relinquish active locality failed DXE TCG
0x12 TIS wait command ready failed (prepare to send) DXE TCG
0x12 TIS abort send command due to timeout DXE TCG
0x12 TIS abort sendAndGo command due to timeout DXE TCG
0x04 TIS wait bit set failed before send last byte DXE TCG
0x12 TIS abort command due to timeout before send last 
byteDXE TCG
0x04 TIS wait bit clear failed when...

150Chapter 4
0x1A Initialize DMA command register with these settings: 
1. Memory to memory disabled 2. Channel 0 hold 
address disabled 3. Controller enabled 4. Normal 
timing 5. Fixed priority 6. Late write selection 7. 
DREQ sense active 8. DACK sense active low.LBT Core
0x22 Reset the keyboard. LBT Core
0x40 Test A20 line LBT Core
0x67 Quick initialization of all Application Processors in a 
multi-processor systemLBT Core
0x32 Compute CPU speed. LBT Core
0x69 Initialize the handler for SMM. LBT Core...