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Acer Aspire 7530 Service Guide

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    							Chapter 4141
    USB Failure (Rightside)
    If the rightside USB port fails, perform the following actions one at a time to correct the problem. Do not 
    replace a non-defective FRUs:
    Modem Function Failure
    If the internal Modem fails, perform the following actions one at a time to correct the problem. Do not replace a 
    non-defective FRUs: 
    						
    							142Chapter 4
    Wireless Function Failure
    If the WLAN fails, perform the following actions one at a time to correct the problem. Do not replace a non-
    defective FRUs:
    EasyTouch Button Failure
    If the Acer EasyTouch buttons fail, perform the following actions one at a time to correct the problem. Do not 
    replace a non-defective FRUs: 
    						
    							Chapter 4143
    MediaTouch Button Failure
    If the Acer MediaTouch buttons fail, perform the following actions one at a time to correct the problem. Do not 
    replace a non-defective FRUs:
    Fingerprint Reader Failure
    If the Fingerprint Reader fails, perform the following actions one at a time to correct the problem. Do not 
    replace a non-defective FRUs: 
    						
    							144Chapter 4
    Thermal Unit Failure
    If the Thermal Unit fails, perform the following actions one at a time to correct the problem. Do not replace a 
    non-defective FRUs:
    HDTV Switch Failure
    If the HDTV Switch fails, perform the following actions one at a time to correct the problem. Do not replace a 
    non-defective FRUs: 
    						
    							Chapter 4145
    External Mouse Failure
    If an external Mouse fails, perform the following actions one at a time to correct the problem. 
    1.Try an alternative mouse.
    2.If the mouse uses a wireless connection, insert new batteries and confirm there is a good connection. See 
    the mouse user manual.
    3.If the mouse uses a USB connection, try an alternate USB port.
    4.Try an alternative program to verify mouse operation. Reinstall the program experiencing mouse failure.
    5.Restart the computer.
    6.Remove any recently added hardware and associated software.
    7.Remove any recently added software and reboot.
    8.Restore system and file settings from a known good date using System Restore. 
    If the issue is not fixed, repeat the preceding steps and select an earlier time and date.
    9.Run the Event Viewer to check the events log for errors. For more information see Windows Help and 
    Support.
    10.Roll back the mouse driver to the previous version if updated recently.
    11 .Remove and reinstall the mouse driver.
    12.Check the Device Manager to determine that:
    •The device is properly installed. There are no red Xs or yellow exclamation marks. 
    •There are no device conflicts. 
    •No hardware is listed under Other Devices.
    13.If the Issue is still not resolved, see “Online Support Information” on page 195.
    Other Failures
    If the CRT Switch, Dock, LAN Port, external MIC or Speakers, PCI Express Card, 5-in-1 Card Reader or 
    Volume Wheel fail, perform the following general steps to correct the problem. Do not replace a non-defective 
    FRUs:
    1.Check Drive whether is OK.
    2.Check Test Fixture is ok.
    3.Swap M/B to Try. 
    						
    							146Chapter 4
    Intermittent Problems
    Intermittent system hang problems can be caused by a variety of reasons that have nothing to do with a 
    hardware defect, such as: cosmic radiation, electrostatic discharge, or software errors. FRU replacement 
    should be considered only when a recurring problem exists.
    When analyzing an intermittent problem, do the following:
    1.Run the advanced diagnostic test for the system board in loop mode at least 10 times.
    2.If no error is detected, do not replace any FRU.
    3.If any error is detected, replace the FRU. Rerun the test to verify that there are no more errors. 
    Undetermined Problems
    The diagnostic problems does not identify which adapter or device failed, which installed devices are incorrect, 
    whether a short circuit is suspected, or whether the system is inoperative. 
    Follow these procedures to isolate the failing FRU (do not isolate non-defective FRU).
    NOTE: Verify that all attached devices are supported by the computer.
    NOTE: Verify that the power supply being used at the time of the failure is operating correctly. (See “Power On 
    Issue” on page 130.):
    1.Power-off the computer.
    2.Visually check them for damage. If any problems are found, replace the FRU.
    3.Remove or disconnect all of the following devices:
    •Non-Acer devices
    •Printer, mouse, and other external devices
    •Battery pack
    •Hard disk drive
    •DIMM 
    •CD-ROM/Diskette drive Module
    •PC Cards
    4.Power-on the computer.
    5.Determine if the problem has changed.
    6.If the problem does not recur, reconnect the removed devices one at a time until you find the failing FRU.
    7.If the problem remains, replace the following FRU one at a time. Do not replace a non-defective FRU:
    •System board
    •LCD assembly 
    						
    							Chapter 4147
    POST Codes Tables
    These tables describe the chipset and core POST codes, functions, phases, and components for the POST. 
    Chipset POST Codes
    The following table details the chipset POST codes and functions used in the POST.
    POST CodeFunctionPhaseComponent
    0xA0 MRC Entry PEI chipset/MRC
    0x01 Enable MCHBAR PEI chipset/MRC
    0x02 Check ME existence PEI chipset/MRC
    0x03 Check for DRAM initialization interrupt and reset fail PEI chipset/MRC
    0x04 Determine the system Memory type based on first 
    populated socketPEI chipset/MRC
    0x05 Verify all DIMMs are DDR2 and SO-DIMMS, which 
    are unbufferedPEI chipset/MRC
    0x06 Verify all DIMMs are Non-ECC PEI chipset/MRC
    0x07 Verify all DIMMs are single or double sided and not 
    mixedPEI chipset/MRC
    0x08 Verify all DIMMs are x8 or x16 width PEI chipset/MRC
    0x09 Calculate number of Row and Column bits PEI chipset/MRC
    0x10 Calculate number of banks for each DIMM PEI chipset/MRC 
    0x11 Determine raw card type PEI chipset/MRC
    0x12 Find a common CAS latency between the DIMMS 
    and the MCHPEI chipset/MRC
    0x13 Determine the memory frequency and CAS latency 
    to programPEI chipset/MRC
    0x14 Determine the smallest common timing value for all 
    DIMMSPEI chipset/MRC
    0x17 Power management resume PEI chipset/MRC
    0x18 Program DRAM type (DDR2/DDR3) and Power up 
    sequencePEI chipset/MRC
    0x19 Program the correct system memory frequency PEI chipset/MRC
    0x20 Program the correct Graphics memory frequency PEI chipset/MRC
    0x21 Early DRC initialization PEI chipset/MRC
    0x22 Program the DRAM Row Attributes and DRAM Row 
    Boundary registers PRE JEDEC.PEI chipset/MRC
    0x23 Program the RCOMP SRAM registers PEI chipset/MRC
    0x24 Program DRAM type (DDR2/DDR3) and Power up 
    sequencePEI chipset/MRC
    0x25 Program the DRAM Timing PEI chipset/MRC
    0x26 Program the DRAM Bank Architecture register PEI chipset/MRC
    0x27 Enable all clocks on populated rows PEI chipset/MRC
    0x28 Program MCH ODT PEI chipset/MRC
    0x29 Program tRD PEI chipset/MRC
    0x30 Miscellaneous Pre JEDEC steps PEI chipset/MRC
    0x31 Program clock crossing registers PEI chipset/MRC 
    						
    							148Chapter 4
    0x32 Program the Egress port timings PEI chipset/MRC
    0x33 Program the Memory IO registers PEI chipset/MRC
    0x34 Perform steps required before JEDEC PEI chipset/MRC
    0x35 Perform JEDEC memory initialization for all memory 
    rowsPEI chipset/MRC
    0x36 Setup DRAM control register for normal operation 
    and enablePEI chipset/MRC
    0x37 Do ZQ calibration for DDR3 PEI chipset/MRC
    0x38 Perform final Dra/Drb programming, Set the mode of 
    operation for the memory channelsPEI chipset/MRC
    0x39 Set Enhanced addressing mode for each channel PEI chipset/MRC
    0x40 Perform steps required after JEDEC init PEI chipset/MRC
    0x41 Program the receive enable reference timing control 
    registerPEI chipset/MRC
    0x42 Post receive enable initialization PEI chipset/MRC
    0x43 Enable sense amps. Reset read/write DQS pointers PEI chipset/MRC
    0x44 Perform ME steps PEI chipset/MRC
    0x45 Clear DRAM initialization bit in the ICH. PEI chipset/MRC
    0x46 Program Thermal Management PEI chipset/MRC
    0x47 Program TS on DIMM PEI chipset/MRC
    0x48 Program TS on Board PEI chipset/MRC
    0xAF Exit MRC PEI chipset/MRC
    0xE0 #define MEM_ERR_BAD_DIMM (S11) PEI chipset/MRC
    0xE1 #define MEM_ERR_ECC_DIMM (S06) PEI chipset/MRC
    0xE2 #define MEM_ERR_SIDES (S07) PEI chipset/MRC
    0xE3 #define MEM_ERR_WIDTH (S08, S10) PEI chipset/MRC
    0xE4 #define MEM_ERR_TRFC (FindTrasTrpTrcd) PEI chipset/MRC
    0xE5 #define MEM_ERR_CAS_LATENCY (S12, S13) PEI chipset/MRC
    0xE6 #define MEM_ERR_REFRESH (ProgDrt) PEI chipset/MRC
    0xE7 #define MEM_ERR_BL8 (S14) PEI chipset/MRC
    0xE9 #define MEM_ERR_FREQUENCY (findTCLTacTClk, 
    S13, S12, ProgramGraphicsFrequency, 
    ProgMchOdt, GetPlatformData)PEI chipset/MRC
    0xEA #define MEM_ERR_SIZE (S14) PEI chipset/MRC
    0xEC #define MEM_ERR_TRAS (FindTrasTrpTrcd) PEI chipset/MRC
    0xED #define MEM_ERR_TRP (FindTrasTrpTrcd) PEI chipset/MRC
    0xEE #define MEM_ERR_TRCD (FindTrasTrpTrcd) PEI chipset/MRC
    0xEF #define MEM_ERR_TWR (FindTrasTrpTrcd) PEI chipset/MRC
    0xF0 #define MEM_ERR_RCVEN_FINDLOW 
    (CalibrateRcvenForGroup)PEI chipset/MRC
    0xF1 #define MEM_ERR_RCVEN_FINDEDGE 
    (CalibrateRcvenForGroup)PEI chipset/MRC
    0xF2 #define MEM_ERR_RCVEN_FINDPREAMBLE 
    (CalibrateRcvenForGroup)PEI chipset/MRC
    0xF6 #define MEM_ERR_RCVEN_PREAMBLEEDGE 
    (CalibrateRcvenForGroup)PEI chipset/MRC
    POST CodeFunctionPhaseComponent 
    						
    							Chapter 4149
    Core POST Codes
    The following table details the core POST codes and functions used in the POST. 0xF3 #define MEM_ERR_RCVEN_FINDCENTER 
    (CalibrateRcvenForGroup)PEI chipset/MRC
    0xFZ #define MEM_ERR_TYPE (S11, S04) PEI chipset/MRC
    0xF5 #define MEM_ERR_RAWCARD (S11) PEI chipset/MRC
    0xFA #define MEM_ERR_SFF (ProgWrioDll) PEI chipset/MRC
    0xFB #define MEM_ERR_THERMAL (ProgramThrottling) PEI chipset/MRC
    0xA0xx Launch BIOS ACMSclean PEI chipset/TXT
    0xA4xx Launch BIOS ACMScheck PEI chipset/TXT
    0xE5 Wait for ME ready DXE HECI/iAMT
    0xE6 ME Ready DXE HECI/iAMT
    POST CodeFunctionPhaseComponent
    0x00 Early Microcode update for CAR CEI / SEC Core
    0x01 Enable CAR CEI / SEC Core
    0x02 CAR Done, initial stack CEI / SEC Core
    0xEE unknown CPU ID to load uCode CEI / SEC CPU
    0xEF unknown DT CPU to load uCode CEI / SEC CPU
    0xnn File count found in a volume PEI Core
    0x11 Debug Test driver for debug test PPI 1 (If install 
    debugTest driver)PEI Core
    0x22 Debug Test driver for debug test PPI 2 (If install 
    debugTest driver)PEI Core
    0x33 Debug Test driver for debug test PPI 3 (If install 
    debugTest driver)PEI Core
    0x44 Entry point of loadfile PEI Core
    0x88 Entry point of apMuLoader PEI Core
    0x80 A PEIM found PEI Core
    0x82 PEIM not dispatched yet PEI Core
    0x84 PEIM satisfies depex PEI Core
    0x86 Image loaded but fail on security PEI Core
    0x88 Executing a PEIM PEI Core
    0x8A Processing notify event for newly installed PPI PEI Core
    0x8C Handing off to next phase (DXE) PEI Core
    0x8F Fail to hand off to next phase, system halt PEI Core
    0x90 All PEIM dispatched! Going to DxeIpl PEI Core
    0xCC AP Micro-code update PEI Core
    0x20 S3 resume entry S3 resume Core
    0x21 Start running Boot-time bootscripts S3 resume Core
    0x22 Start running Run-time bootscripts S3 resume Core
    0x23 End of S3 resume, jump back to Waking vector S3 resume Core
    0x80 Initialize the chipset Crisis Recovery Core
    0x81 Initialize the bridge Crisis Recovery Core
    POST CodeFunctionPhaseComponent 
    						
    							150Chapter 4
    0x82 Initialize the CPU Crisis Recovery Core
    0x89 Set Huge Segment Crisis Recovery Core
    0x83 Initialize system timer Crisis Recovery Core
    0x84 Initialize system I/O Crisis Recovery Core
    0x88 Initialize Multi Processor Crisis Recovery Core
    0x8A Initialize OEM special code Crisis Recovery Core
    0x8B Initialize PIC and DMA Crisis Recovery Core
    0x8C Initialize Memory type Crisis Recovery Core
    0x8D Initialize Memory size Crisis Recovery Core
    0x8F Initialize SMM Crisis Recovery Core
    0x90 System memory test Crisis Recovery Core
    0x91 Initialize interrupt vectors Crisis Recovery Core
    0x92 Initialize Run Time Clock Crisis Recovery Core
    0x99 Initialize security Crisis Recovery Core
    0x93 Initialize video Crisis Recovery Core
    0x94 Output one beep Crisis Recovery Core
    0x98 USB Initialization Crisis Recovery Core
    0x95 Initialize the installed boot devices Crisis Recovery Core
    0x96 Clear Huge segment Crisis Recovery Core
    0x97 Boot Crisis Disk Crisis Recovery Core
    0x20 DXE starts DXE Core
    0x30 BIOSPSM DXE Core
    0x02 BIOSBlockIO DXE Core
    0x00 BIOSPSM Exception Handler - Divide error BIOSPSM Core
    0x38 Cannot locate LegacyRegion DXE BIOSPSM Core
    0xB1 ACPISupport driver Installed DXE Core
    0xE0 BDS Entry DXE Core
    0x07 IA32 variable driver entry DXE Core
    0x0D conspliter driver entry DXE Core
    0x10 partition driver entry DXE Core
    0x49 pciRootBridge driver entry DXE Core
    0xC6 pciBusDriver entry DXE Core
    0xE0 Go to legacy BIOS or BDS Entry Point DXE Core
    0x90 Start Image DXE Core
    0x90 Start Image Successfully DXE Core
    0x90 Start Image Failed DXE Core
    0x33 Debug Test driver for debug test PPI 1 DXE Core
    0x22 Debug Test driver for debug test PPI 2 DXE Core
    0x11 Debug Test driver for debug test PPI 3 DXE Core
    0x02 Invalid event # for measuring Separator Event DXE TCG
    0x02 Invalid event # for measuring Separator Event DXE TCG
    0x02 PCR Index over limit (PCR > 23) DXE TCG
    0x02 TCG copy memory failed DXE TCG
    POST CodeFunctionPhaseComponent 
    						
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