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Acer Aspire 5530 Service Guide

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    							Chapter 4161
    POST Codes Tables
    These tables describe the POST codes, functions, phases, and components for the POST.
    Chipset POST Codes
    The following table details the chipset POST codes and functions used in the POST.
    CodeBeepsPOST Routine Description
    02h Verify Real Mode
    03h Disable Non-Maskable Interrupt (NMI)
    04h Get CPU type
    06h Initialize system hardware
    08h Initialize chipset with initial POST values
    09h Set IN POST flag
    0Ah Initialize CPU registers
    0Bh Enable CPU cache
    0Ch Initialize caches to initial POST values
    0Eh Initialize I/O component
    0Fh Initialize the local bus IDE
    10h Initialize Power Management
    11h Load alternate registers with initial POST values
    12h Restore CPU control word during warm boot
    13h Initialize PCI Bus Mastering devices
    14h Initialize keyboard controller
    16h 1-2-2-3 BIOS ROM checksum
    17h Initialize cache before memory autosize
    18h 8254 timer initialization
    1Ah 8237 DMA controller initialization
    1Ch Reset Programmable Interrupt Controller
    20h 1-3-1-1 Test DRAM refresh
    22h 1-3-1-3 Test 8742 Keyboard Controller
    24h Set ES segment register to 4 GB
    26h Enable A20 line
    28h Autosize DRAM
    29h Initialize POST Memory Manager
    2Ah Clear 512 KB base RAM
    2Ch 1-3-4-1 RAM failure on address line xxxx*
    2Eh 1-3-4-3 RAM failure on data bits xxxx* of low byte of memory bus
    2Fh Enable cache before system BIOS shadow
    30h 1-4-1-1 RAM failure on data bits xxxx* of high byte of memory bus
    32h Test CPU bus-clock frequency
    33h Initialize Phoenix Dispatch Manager
    36h Warm start shut down
    38h Shadow system BIOS ROM
    3Ah Autosize cache 
    						
    							162Chapter 4
    3Ch Advanced configuration of chipset registers
    3Dh Load alternate registers with CMOS values
    42h Initialize interrupt vectors
    45h POST device initialization
    46h 2-1-2-3 Check ROM copyright notice
    48h Check video configuration against CMOS
    49h Initialize PCI bus and devices
    4Ah Initialize all video adapters in system
    4Bh QuietBoot start (optional)
    4Ch Shadow video BIOS ROM
    4Eh Display BIOS copyright notice
    50h Display CPU type and speed
    51h Initialize EISA board
    52h Test keyboard
    54h Set key click if enabled
    58h 2-2-3-1 Test for unexpected interrupts
    59h Initialize POST display service
    5Ah Display prompt Press F2 to enter SETUP
    5Bh Disable CPU cache
    5Ch Test RAM between 512 and 640 KB
    60h Test extended memory
    62h Test extended memory address lines
    64h Jump to UserPatch1
    66h Configure advanced cache registers
    67h Initialize Multi Processor APIC
    68h Enable external and CPU caches
    69h Setup System Management Mode (SMM) area
    6Ah Display external L2 cache size
    6Bh Load custom defaults (optional)
    6Ch Display shadow-area message
    6Eh Display possible high address for UMB recovery
    70h Display error messages
    72h Check for configuration errors
    76h Check for keyboard errors
    7Ch Set up hardware interrupt vectors
    7Eh Initialize coprocessor if present
    80h Disable onboard Super I/O ports and IRQs
    81h Late POST device initialization
    82h Detect and install external RS232 ports
    83h Configure non-MCD IDE controllers
    84h Detect and install external parallel ports
    85h Initialize PC-compatible PnP ISA devices
    86h Re-initialize onboard I/O ports.
    CodeBeepsPOST Routine Description 
    						
    							Chapter 4163
    87h Configure Motherboard Configurable Devices (optional)
    88h Initialize BIOS Data Area
    89h Enable Non-Maskable Interrupts (NMIs)
    8Ah Initialize Extended BIOS Data Area
    8Bh Test and initialize PS/2 mouse
    8Ch Initialize floppy controller
    8Fh Determine number of ATA drives (optional)
    90h Initialize hard-disk controllers
    91h Initialize local-bus hard-disk controllers
    92h Jump to UserPatch2
    93h Build MPTABLE for multi-processor boards
    95h Install CD ROM for boot
    96h Clear huge ES segment register
    97h Fixup Multi Processor table
    98h 1-2 Search for option ROMs. One long, two short beeps on checksum failure
    99h Check for SMART Drive (optional)
    9Ah Shadow option ROMs
    9Ch Set up Power Management
    9Dh Initialize security engine (optional)
    9Eh Enable hardware interrupts
    9Fh Determine number of ATA and SCSI drives
    A0h Set time of day
    A2h Check key lock
    A4h Initialize Typematic rate
    A8h Erase F2 prompt
    AAh Scan for F2 key stroke
    ACh Enter SETUP
    AEh Clear Boot flag
    B0h Check for errors
    B2h POST done - prepare to boot operating system
    B4h 1 One short beep before boot
    B5h Terminate QuietBoot (optional)
    B6h Check password (optional)
    B9h Prepare Boot
    BAh Initialize DMI parameters
    BBh Initialize PnP Option ROMs
    BCh Clear parity checkers
    BDh Display MultiBoot menu
    BEh Clear screen (optional)
    BFh Check virus and backup reminders
    C0h Try to boot with INT 19
    C1h Initialize POST Error Manager (PEM)
    C2h Initialize error logging
    CodeBeepsPOST Routine Description 
    						
    							164Chapter 4
    * If the BIOS detects error 2C, 2E, or 30 (base 512K RAM error), it displays an additional word-bitmap (xxxx) 
    indicating the address line or bits that failed. For example, 2C 0002 means address line 1 (bit one set) has 
    failed. 2E 1020 means data bits 12 and 5 (bits 12 and 5 set) have failed in the lower 16 bits. Note that error 30 
    cannot occur on 386SX systems because they have a 16 rather than 32-bit bus. The BIOS also sends the 
    bitmap to the port-80 LED display. It first displays the check point code, followed by a delay, the high-order 
    byte, another delay, and then the low-order byte of the error. It repeats this sequence continuously. C3h Initialize error display function
    C4h Initialize system error handler
    C5h PnPnd dual CMOS (optional)
    C6h Initialize notebook docking (optional)
    C7h Initialize notebook docking late
    C8h Force check (optional)
    C9h Extended checksum (optional)
    D2h Unknown interrupt
    CodeBeepsFor Boot Block in Flash ROM
    E0h Initialize the chipset
    E1h Initialize the bridge
    E2h Initialize the CPU
    E3h Initialize system timer
    E4h Initialize system I/O
    E5h Check force recovery boot
    E6h Checksum BIOS ROM
    E7h Go to BIOS
    E8h Set Huge Segment
    E9h Initialize Multi Processor
    EAh Initialize OEM special code
    EBh Initialize PIC and DMA
    ECh Initialize Memory type
    EDh Initialize Memory size
    EEh Shadow Boot Block
    EFh System memory test
    F0h Initialize interrupt vectors
    F1h Initialize Run Time Clock
    F2h Initialize video
    F3h Initialize System Management Mode
    F4h 1 Output one beep before boot
    F5h Boot to Mini DOS
    F6h Clear Huge Segment
    F7h Boot to Full DOS
    CodeBeepsPOST Routine Description 
    						
    							Chapter 5165
    Jumper and Connector Locations
    Top View
    ItemDescriptionItemDescription
    JLVDS1 LCD Connector JP13  FP/B Connector 
    JP23 Acer backlight Connector JP27  Sub-Woofer Connector 
    JP16 Power/B Connector JP9  USB/B Connector 
    JP8  TV/B Connector JP10  Bluetooth Connector 
    JP21 Fun/B Connector  JMDC1  MDC Connector 
    JP14 Media/B Connector  JEXP1  Express Card Socket 
    JP19 Speaker (Left) Connector  JP17  BTN/B Connector 
    JP20 Speaker (Right) Connector  SW1  Touch pad (right) Button 
    JP15  Internal Keyboard Connector  SW2  Touch  pad  (left)  Button 
    JP7  Touch Pad Connector  U10  South Bridge 
    Chapter 5 
    						
    							166Chapter 5
    Bottom View
    ItemDescriptionItemDescription
    PJP1 AC-IN Connector JSATA2 HDD Connector
    JDOCK1 Dock Connector JMINI2 TV-Tuner Card Connector
    JRJ45 RJ45 Connector JMINI1 Wireless Card Connector
    JMXM1 MXM Board Connector JSATA1 ODD Connector
    JCRT1 CRT Connector JDIMM2Memory DIMM2 Connector
    JHDMI1 HDMI Connector JDIMM1 Memory DIMM1 Connector
    JUSB1 USB Connector PJP2 Battery Connector
    JUSB2 USB Connector JCPU1 CPU Socket
    JLINE1 Line-In Jack U25 North Bridge
    JMIC1 MIC-In Jack U37 Volume control wheel
    JHP1 Head-Phone Connector IR1 IR receiver
    JREAD1 Card Reader Socket 
    						
    							Chapter 2167
    Clearing Password Check and BIOS Recovery
    This section provide you the standard operating procedures of clearing password and BIOS recovery for 
    Aspire 5530. Aspire 5530 provide one Hardware Open Gap on main board for clearing password check, and 
    one Hotkey for enabling BIOS Recovery.
    Clearing Password Check
    Hardware Open Gap Description
    Steps for Clearing BIOS Password Check
    If users set BIOS Password (Supervisor Password and/or User Password) for a security reason, BIOS will ask 
    the password during systems POST or when systems enter to BIOS Setup menu. However, once it is 
    necessary to bypass the password check, users need to short the HW Gap to clear the password by the 
    following steps:
    •Power Off a system, and remove HDD, AC and Battery from the machine.
    •Open the back cover of the machine, and find out the HW Gap on M/B as picture.
    •Use an electric conductivity tool to short the two points of the HW Gap.
    •Plug in AC, keep the short condition on the HW Gap, and press Power Button to power on the 
    system till BIOS POST finish. Then remove the tool from the HW Gap.
    •Restart system. Press F2 key to enter BIOS Setup menu.
    •If there is no Password request, BIOS Password is cleared. Otherwise, please follow the steps and 
    try again.
    NOTE: The steps are only for clearing BIOS Password (Supervisor Password and User Password).
    ItemDescription
    J1 Clear CMOS Jumper 
    						
    							168Chapter 5
    BIOS Recovery by Crisis Disk
    BIOS Recovery Boot Block:
    BIOS Recovery Boot Block is a special block of BIOS. It is used to boot up the system with minimum BIOS 
    initialization. Users can enable this feature to restore the BIOS firmware to a successful one once the previous 
    BIOS flashing process failed.
    BIOS Recovery Hotkey:
    The system provides a function hotkey: Fn+Esc, for enable BIOS Recovery process when system is powered 
    on during BIOS POST. To use this function, it is strongly recommended to have the AC adapter and Battery 
    present. If this function is enabled, the system will force the BIOS to enter a special BIOS block, called Boot 
    Block.
    Steps for BIOS Recovery by Crisis Disk:
    Before doing this, one Crisis Diskette should be prepared ready in hand. The Crisis Diskette could be made by 
    executing the Crisis Disk program in another system with Windows XP OS.
    Follow the steps below:
    1.Power Off failed system.
    2.Attach a USB floppy drive to the failed system. 
    3.Copy jalb028.wph to tools folder and rename it as BIOS.wph.
    4.Execute wincris.exe to start the Crisis Disk Build.
    5.Select Removable and click Start.
    6.Select Format Disk and click Start. 
    						
    							Chapter 2169
    A progress screen displays.
    7.The following message displays when the Crisis Diskette is created successfully.
    8.Click OK to complete the process.
    9.Insert the Crisis Disk in to the USB floppy drive attached to the BIOS flash failed system.
    10.In the power-off state, press and hold Fn+Esc then press the Power button. 
    The system powers on and the Crisis BIOS Recovery process begins.
    BIOS Boot Block begins restoring the BIOS code from the Crisis floppy disk to BIOS ROM on the failed 
    systems.
    When the Crisis flash process is finished, the system restarts with a workable BIOS. 
    Update to the latest version BIOS for the system using the regular BIOS flashing process. 
    						
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