Acer Aspire 4230 Service Guide
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Chapter 4131 External Mouse Failure If an external Mouse fails, perform the following actions one at a time to correct the problem. 1.Try an alternative mouse. 2.If the mouse uses a wireless connection, insert new batteries and confirm there is a good connection. See the mouse user manual. 3.If the mouse uses a USB connection, try an alternate USB port. 4.Try an alternative program to verify mouse operation. Reinstall the program experiencing mouse failure. 5.Restart the computer. 6.Remove any recently...
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132Chapter 4 Intermittent Problems Intermittent system hang problems can be caused by a variety of reasons that have nothing to do with a hardware defect, such as: cosmic radiation, electrostatic discharge, or software errors. FRU replacement should be considered only when a recurring problem exists. When analyzing an intermittent problem, do the following: 1.Run the advanced diagnostic test for the system board in loop mode at least 10 times. 2.If no error is detected, do not replace any FRU. 3.If any...
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Chapter 4133 POST Codes Tables These tables describe the chipset and core POST codes, functions, phases, and components for the POST. Chipset POST Codes The following table details the chipset POST codes and functions used in the POST. POST CodeFunctionPhaseComponent 0xA0 MRC Entry PEI chipset/MRC 0x01 Enable MCHBAR PEI chipset/MRC 0x02 Check ME existence PEI chipset/MRC 0x03 Check for DRAM initialization interrupt and reset fail PEI chipset/MRC 0x04 Determine the system Memory type based on first...
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134Chapter 4 0x32 Program the Egress port timings PEI chipset/MRC 0x33 Program the Memory IO registers PEI chipset/MRC 0x34 Perform steps required before JEDEC PEI chipset/MRC 0x35 Perform JEDEC memory initialization for all memory rowsPEI chipset/MRC 0x36 Setup DRAM control register for normal operation and enablePEI chipset/MRC 0x37 Do ZQ calibration for DDR3 PEI chipset/MRC 0x38 Perform final Dra/Drb programming, Set the mode of operation for the memory channelsPEI chipset/MRC 0x39 Set Enhanced...
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Chapter 4135 Core POST Codes The following table details the core POST codes and functions used in the POST. 0xF3 #define MEM_ERR_RCVEN_FINDCENTER (CalibrateRcvenForGroup)PEI chipset/MRC 0xFZ #define MEM_ERR_TYPE (S11, S04) PEI chipset/MRC 0xF5 #define MEM_ERR_RAWCARD (S11) PEI chipset/MRC 0xFA #define MEM_ERR_SFF (ProgWrioDll) PEI chipset/MRC 0xFB #define MEM_ERR_THERMAL (ProgramThrottling) PEI chipset/MRC 0xA0xx Launch BIOS ACMSclean PEI chipset/TXT 0xA4xx Launch BIOS ACMScheck PEI chipset/TXT 0xE5...
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136Chapter 4 0x82 Initialize the CPU Crisis Recovery Core 0x89 Set Huge Segment Crisis Recovery Core 0x83 Initialize system timer Crisis Recovery Core 0x84 Initialize system I/O Crisis Recovery Core 0x88 Initialize Multi Processor Crisis Recovery Core 0x8A Initialize OEM special code Crisis Recovery Core 0x8B Initialize PIC and DMA Crisis Recovery Core 0x8C Initialize Memory type Crisis Recovery Core 0x8D Initialize Memory size Crisis Recovery Core 0x8F Initialize SMM Crisis Recovery Core 0x90 System...
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Chapter 4137 0x09 TCG log event failed DXE TCG 0x09 Setup event log failed DXE TCG 0x12 TIS set active locality failed DXE TCG 0x12 TIS relinquish active locality failed DXE TCG 0x12 TIS wait command ready failed (prepare to send) DXE TCG 0x12 TIS abort send’ command due to timeout DXE TCG 0x12 TIS abort sendAndGo command due to timeout DXE TCG 0x04 TIS wait bit set failed before send last byte DXE TCG 0x12 TIS abort command due to timeout before send last byteDXE TCG 0x04 TIS wait bit clear failed when...
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138Chapter 4 0x1A Initialize DMA command register with these settings: 1. Memory to memory disabled 2. Channel 0 hold address disabled 3. Controller enabled 4. Normal timing 5. Fixed priority 6. Late write selection 7. DREQ sense active 8. DACK sense active low.LBT Core 0x22 Reset the keyboard. LBT Core 0x40 Test A20 line LBT Core 0x67 Quick initialization of all Application Processors in a multi-processor systemLBT Core 0x32 Compute CPU speed. LBT Core 0x69 Initialize the handler for SMM. LBT Core...
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Chapter 4139 0x4C Shadow video BIOS ROM if specified by Setup, and CMOS is valid and the previous boot was OK.LBT Core 0x59 Register POST Display Services, fonts, and languages with the POST Dispatch Manager.LBT Core 0x57 Initialize 1394 Firewire LBT Core 0xD6 Initialize PC card LBT Core 0x58 Test for unexpected interrupts. First do an STI for hot interrupts. Secondly, test the NMI for an unexpected interrupt. Thirdly, enable the parity checkers and read from memory, checking for an unexpected...
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140Chapter 4 0x6A Display external cache size on the screen if it is non- zero.LBT Core 0x6C Display shadow message LBT Core 0xCA post EISA init LBT Core 0x70 Check flags in CMOS and in the TrustedCore data area for errors detected during POST. Display error messages on the screen.LBT Core 0x72 Check status bits to see if configuration problems were detected. If so, display error messages on the screen.LBT Core 0x4F Initialize MultiBoot. Allocate memory for old and new MultiBoot history tables.LBT...